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37. 
Cover image for Introduction to Embedded System Design Using Field Programmable Gate Arrays
Introduction to Embedded System Design Using Field Programmable Gate Arrays
Author 
Dubey, Rahul. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-84882-016-6
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38. 
Cover image for High-Level Synthesis From Algorithm to Digital Circuit
High-Level Synthesis From Algorithm to Digital Circuit
Author 
Coussy, Philippe. editor. Morawiec, Adam. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-8588-8
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39. 
Cover image for Practical Problems in VLSI Physical Design Automation
Practical Problems in VLSI Physical Design Automation
Author 
Lim, Sung Kyu. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-6627-6
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40. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings
Author 
Azémard, Nadine. editor. Svensson, Lars. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-3-540-74442-9
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41. 
Cover image for Layoutsynthese elektronischer Schaltungen — Grundlegende Algorithmen für die Entwurfsautomatisierung
Layoutsynthese elektronischer Schaltungen — Grundlegende Algorithmen für die Entwurfsautomatisierung
Author 
Lienig, Jens. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/3-540-29942-4
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42. 
Cover image for A Roadmap for Formal Property Verification
A Roadmap for Formal Property Verification
Author 
DasGupta, Pallab. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-4758-9
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43. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings
Author 
Vounckx, Johan. editor. Azemard, Nadine. editor. Maurine, Philippe. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/11847083
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44. 
Cover image for Taxonomies for the Development and Verification of Digital Systems
Taxonomies for the Development and Verification of Digital Systems
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Bailey, Brian. editor. Martin, Grant. editor. Anderson, Thomas. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/b104217
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45. 
Cover image for Control Theory
Control Theory
Author 
Leigh, J. R.
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http://dx.doi.org/10.1049/PBCE064E
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