Design of cost-efficient interconnect processing units Spidergon STNoC
by
 
Coppola, Marcello.

Title
: 
Design of cost-efficient interconnect processing units Spidergon STNoC

Author
: 
Coppola, Marcello.

ISBN
: 
9781420044720

Publication Information
: 
Boca Raton [Fla.] : CRC Press, c2009.

Physical Description
: 
xxi, 263 p. : ill.

Series
: 
System-on-chip design and technologies

Series Title
: 
System-on-chip design and technologies

Contents
: 
1. Towards multicores : technology and software complexity -- 2. On-chip bus vs. network-on-chip -- 3. NoC topology -- 4. The Spidergon STNoC -- 5. SoC and NoC design methodology and tools -- 6. Conclusions and future work -- References -- Index.

Corporate Subject
: 
ST Microelectronics.

Subject Term
: 
Networks on a chip.
 
Microprocessors.

Added Author
: 
Coppola, Marcello.

Electronic Access
: 
Distributed by publisher. Purchase or institutional license may be required for access.


LibraryMaterial TypeItem BarcodeShelf Number[[missing key: search.ChildField.HOLDING]]Status
Online LibraryE-Book287752-1001ONLINEElektronik Kütüphane