Designing network on-chip architectures in the nanoscale era
by
 
Flich, Jose.

Title
Designing network on-chip architectures in the nanoscale era

Author
Flich, Jose.

ISBN
9781439837115

Publication Information
Boca Raton, Fla. : Chapman and Hall/CRC, 2011.

Physical Description
xxxviii, 490 p. : ill. (some col.).

Series
Chapman & Hall/CRC computational science series

Series Title
Chapman & Hall/CRC computational science series

Contents
1. NoC technology -- 2. The industrial perspective -- 3. Upcoming trends.

Abstract
"Paving the way for the use of network on-chip architectures in 2015 platforms, this book presents the industrial requirements for such long-term platforms as well as the main research findings for technology-aware architecture design. It covers homogeneous design techniques and guidelines, including the solutions that are most appealing to the industry and best suited to meet the requirements of on-chip integration. Each chapter deals with a specific key architecture design, including fault tolerant design, topology selection, dynamic voltage and frequency scaling, synchronization, network on-chip resources exposed to the architecture, routing algorithms, and collective communication"-- Provided by publisher.

Subject Term
Networks on a chip.

Added Author
Flich, Jose.
 
Bertozzi, Davide.

Electronic Access
Distributed by publisher. Purchase or institutional license may be required for access.


LibraryMaterial TypeItem BarcodeShelf Number[[missing key: search.ChildField.HOLDING]]Status
Online LibraryE-Book291553-1001ONLINEElektronik Kütüphane