Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog
by
 
Taraate, Vaibbhav. author.

Title
: 
Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog

Author
: 
Taraate, Vaibbhav. author.

ISBN
: 
9789811087769

Edition
: 
1st ed. 2019.

Physical Description
: 
XXI, 307 p. 263 illus., 196 illus. in color. online resource.

Subject Term
: 
Electronic circuits.
 
Microprogramming .
 
Logic design.

Added Corporate Author
: 
SpringerLink (Online service)

Electronic Access
: 
https://doi.org/10.1007/978-981-10-8776-9


LibraryMaterial TypeItem BarcodeShelf Number[[missing key: search.ChildField.HOLDING]]Status
Online LibraryE-Book484875-1001ONLINEElektronik Kütüphane