chapter 1 Design Flows -- chapter 2 Logic Synthesis -- chapter 3 Power Analysis and Optimization from Circuit to Register-Transfer Levels -- chapter 4 Equivalence Checking -- chapter 5 Digital Layout — Placement -- chapter 6 Static Timing Analysis -- chapter 7 Structured Digital Design -- chapter 8 Routing -- chapter 9 Exploring Challenges of Libraries for Electronic Design -- chapter 10 Design Closure -- chapter 11 Tools for Chip-Package Codesign -- chapter 12 Design Databases -- chapter 13 FPGA Synthesis and Physical Design -- chapter 14 Simulation of Analog and RF Circuits and Systems -- chapter 15 Simulation and Modeling for Analog and Mixed-Signal Integrated Circuits -- chapter 16 Layout Tools for Analog Integrated Circuits and Mixed-Signal Systems-on-Chip -- chapter 17 Design Rule Checking -- chapter 18 Resolution Enhancement Techniques and Mask Data Preparation -- chapter 19 Design for Manufacturability in the Nanometer Era -- chapter 20 Design and Analysis of Power Supply Networks -- chapter 21 Noise Considerations in Digital ICs -- chapter 22 Layout Extraction -- chapter 23 Mixed-Signal Noise Coupling in System-on-Chip Design -- chapter 24 Process Simulation -- chapter 25 Device Modeling —From Physics to Electrical Parameter Extraction -- chapter 26 High-Accuracy Parasitic Extraction.