Search Results for Integrated circuits -- Verification.

Skip to:Search Results

|

|

|

|

|

|

|

Remember to clear the cache and close the browser window.

Search Limit

Rooms Restriction Values

13

Search Field

Target Value

Limit Value

Restriction Value

Search For:

Advanced Search

Limit Search Results

Author

Andrews, Jason R.

(1)

(1)

Foster, Harry, 1956-

(1)

Fujita, Masahiro, 1956-

(1)

Ghosh, Indradeep, 1970-

(1)

Harris, Ian G..

(1)

(1)

Lavagno, Luciano, 1959-

(1)

(1)

Martin, Grant (Grant Edmund)

(1)

Meyer, Andreas (Andreas S.)

(1)

Perry, Douglas L.

(1)

Pradhan, Dhiraj K..

(1)

(1)

Scheffer, Louis Kossuth.

(1)

Thornton, Mitchell Aaron.

(1)

Yoeli, Michael, 1917-

(1)

Language

(9)

Publication Date

-

(2)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

Subject

Integrated circuits -- Verification.

(8)

Computer software -- Verification.

(2)

Formal methods (Computer science)

(2)

Asynchrones Schaltwerk.

(1)

Computerarchitektur.

(1)

Electronic books.

(1)

Electronic circuits -- Testing.

(1)

Geschwindigkeitsunabhängigkeit.

(1)

Hardwareverifikation.

(1)

Integrated circuits -- Computer simulation.

(1)

Integrated circuits -- Computer-aided design.

(1)

Integrated circuits -- Verification -- Data processing.

(1)

Integrated circuits -- Very large scale integration.

(1)

Integrierte Schaltung.

(1)

LOTOS (Computer program language)

(1)

(1)

Sequential machine theory.

(1)

Switching circuits.

(1)

Systems on a chip -- Testing.

(1)

Systems on a chip.

(1)

Material Type

Shelf Location

Electronic Library

Library

{sortLabel}

	{facetName}	{results}

	{displayName}	{count}
{error}

Switch to list view

Switch to thumbnail view

9 Results Found

Subscribe to search results

1

000000000DEFAULT

Print

Select a list

Make this your default list.

The following items were successfully added.

There was an error while adding the following items. Please try again.

One or more items could not be added because you are not logged in.

1.

Cover image for Applied formal verification

Applied formal verification

Applied formal verification

Author

Perry, Douglas L. Foster, Harry, 1956-

Preferred Shelf Number

ONLINE

Electronic Access

Subscription required

Format:

Availability

Online Library~1

Available:
Copies:

2.

Cover image for Digital system verification a combined formal methods and simulation framework

Digital system verification a combined formal methods and simulation framework

Digital system verification a combined formal methods and simulation framework

Author

Li, Lun, 1970- Thornton, Mitchell Aaron.

Preferred Shelf Number

ONLINE

Electronic Access

EBSCOhost http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=440373

Format:

Availability

Online Library~1

Available:
Copies:

3.

Cover image for Practical Design Verification

Practical Design Verification

Practical Design Verification

Author

Pradhan, Dhiraj K.. Harris, Ian G..

Preferred Shelf Number

ONLINE

Electronic Access

Access by subscription

Format:

Availability

Online Library~1

Available:
Copies:

4.

Cover image for Verification techniques for system-level design

Verification techniques for system-level design

Verification techniques for system-level design

Author

Fujita, Masahiro, 1956- Ghosh, Indradeep, 1970- Prasad, Mukul.

Preferred Shelf Number

ONLINE

Electronic Access

ScienceDirect http://www.sciencedirect.com/science/book/9780123706164

Format:

Availability

Online Library~1

Available:
Copies:

5.

Cover image for Verification of systems and circuits using LOTOS, Petri Nets, and CCS

Verification of systems and circuits using LOTOS, Petri Nets, and CCS

Verification of systems and circuits using LOTOS, Petri Nets, and CCS

Author

Yoeli, Michael, 1917- Kol, Rakefet.

Preferred Shelf Number

ONLINE

Electronic Access

Available by subscription from Safari Books Online
Contributor biographical information http://catdir.loc.gov/catdir/enhancements/fy0809/2007033487-b.html
John Wiley http://dx.doi.org/10.1002/9780470253410
Volltext http://proquest.tech.safaribooksonline.de/9780471704492

Format:

Availability

Online Library~1

Available:
Copies:

6.

Cover image for EDA for IC system design, verification, and testing

EDA for IC system design, verification, and testing

EDA for IC system design, verification, and testing

Author

Scheffer, Louis Kossuth. Lavagno, Luciano, 1959- Martin, Grant (Grant Edmund)

Preferred Shelf Number

ONLINE

Electronic Access

Distributed by publisher. Purchase or institutional license may be required for access.

Format:

Availability

Online Library~1

Available:
Copies:

7.

Cover image for Co-verification of hardware and software for ARM SoC design

Co-verification of hardware and software for ARM SoC design

Co-verification of hardware and software for ARM SoC design

Author

Andrews, Jason R.

Preferred Shelf Number

ONLINE

Electronic Access

ScienceDirect http://www.sciencedirect.com/science/book/9780750677301

Format:

Availability

Online Library~1

Available:
Copies:

8.

Cover image for Principles of functional verification

Principles of functional verification

Principles of functional verification

Author

Meyer, Andreas (Andreas S.)

Preferred Shelf Number

ONLINE

Electronic Access

ScienceDirect http://www.sciencedirect.com/science/book/9780750676175

Format:

Availability

Online Library~1

Available:
Copies:

9.

Cover image for Trace theory for automatic hierarchical verification of speed-independent circuits

Trace theory for automatic hierarchical verification of speed-independent circuits

Trace theory for automatic hierarchical verification of speed-independent circuits

Author

Dill, David L.

Preferred Shelf Number

ONLINE

Electronic Access

IEEE Xplore http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6267249

Format:

Availability

Online Library~1

Available:
Copies:

1

Go to:Search Results

|

|

Copyright 2018 Sirsi Corporation - Enterprise Version 5.0.0.11