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Author

Bregni, Stefano.

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Champac, Victor. author.

(1)

Chaudhari, Qasim M..

(1)

Chen, Wai-Kai, 1936-

(1)

Garcia Gervacio, Jose. author.

(1)

Harris, David Money.

(1)

(1)

John Wiley & Sons.

(1)

Kinniment, David.

(1)

Mills, David L.

(1)

Oklobdzija, Vojin G.

(1)

Oklobdzija, Vojin G., ort. yaz.

(1)

Razavi, Behzad.

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Serpedin, Erchin.

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SpringerLink (Online service)

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Wiley InterScience (Online service)

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Timing circuits -- Design and construction.

(6)

Electronic books.

(4)

Synchronization.

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Timing circuits.

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Electronic digital computers -- Power supply.

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High performance computing.

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Low voltage integrated circuits -- Design and construction.

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Memory management (Computer science)

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Synchronous data transmission systems.

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BELLEK YÖNETİMİ (BİLGİSAYAR BİLİMİ)

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Computer multitasking.

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Computer networks.

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Computer science.

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Digital integrated circuits -- Design and construction.

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DÜŞÜK VOLTAJLI ENTEGRE DEVRELER -- ÇİZİM VE YAPIM.

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ELEKTRONİK SAYISAL BİLGİSAYARLAR -- GÜÇ SAĞLAMA.

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Electric power -- Conservation.

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Electrical and Electronics Engineering.

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Embedded computer systems -- Design and construction -- Data processing.

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Frequency synthesizers.

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Integrated circuits -- Design and construction.

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Integrated circuits -- Very large scale integration.

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Integrated circuits, Very large scale integration -- Design and construction.

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Phase-locked loops -- Design and construction.

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Systems engineering.

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Systems on a chip -- Design and construction -- Data processing.

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TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- General.

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TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- Integrated.

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TECHNOLOGY & ENGINEERING / Microwaves

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Timing circuits -- Design and construction -- Data processing.

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Very high speed integrated circuits.

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Wireless sensor networks.

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YÜKSEK BAŞARIMLI HESAPLAMA.

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ZAMAN DEVRELERİ -- ÇİZİM VE YAPIM.

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1.

Cover image for Timing Performance of Nanometer Digital Circuits Under Process Variations

Timing Performance of Nanometer Digital Circuits Under Process Variations

Timing Performance of Nanometer Digital Circuits Under Process Variations

Author

Champac, Victor. author. Garcia Gervacio, Jose. author. SpringerLink (Online service)

Preferred Shelf Number

ONLINE

Electronic Access

https://doi.org/10.1007/978-3-319-75465-9

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Online Library~1

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2.

Cover image for Nanometer frequency synthesis beyond the phase-locked loop

Nanometer frequency synthesis beyond the phase-locked loop

Nanometer frequency synthesis beyond the phase-locked loop

Author

Xiu, Liming.

Preferred Shelf Number

ONLINE

Electronic Access

IEEE Xplore http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6266786

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Online Library~1

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3.

Cover image for Synchronization in Wireless Sensor Networks Parameter Estimation, Performance Benchmarks, and Protocols

Synchronization in Wireless Sensor Networks Parameter Estimation, Performance Benchmarks, and Protocols

Synchronization in Wireless Sensor Networks Parameter Estimation, Performance Benchmarks, and Protocols

Author

Serpedin, Erchin. Chaudhari, Qasim M..

Preferred Shelf Number

ONLINE

Electronic Access

Access by subscription

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Online Library~1

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4.

Cover image for The VLSI handbook

The VLSI handbook

The VLSI handbook

Author

Chen, Wai-Kai, 1936-

Preferred Shelf Number

ONLINE

Electronic Access

Distributed by publisher. Purchase or institutional license may be required for access.

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Online Library~1

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5.

Cover image for Synchronization and arbitration in digital systems

Synchronization and arbitration in digital systems

Synchronization and arbitration in digital systems

Author

Kinniment, David. Wiley InterScience (Online service)

Preferred Shelf Number

ONLINE

Electronic Access

John Wiley http://dx.doi.org/10.1002/9780470517147

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Online Library~1

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6.

Cover image for Computer network time synchronization the network time protocol

Computer network time synchronization the network time protocol

Computer network time synchronization the network time protocol

Author

Mills, David L.

Preferred Shelf Number

ONLINE

Electronic Access

Distributed by publisher. Purchase or institutional license may be required for access.

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7.

Cover image for Modeling embedded systems and SoC's concurrency and time in models of computation

Modeling embedded systems and SoC's concurrency and time in models of computation

Modeling embedded systems and SoC's concurrency and time in models of computation

Author

Jantsch, Axel.

Preferred Shelf Number

ONLINE

Electronic Access

ScienceDirect http://www.sciencedirect.com/science/book/9781558609259

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8.

Cover image for Digital system clocking high performance and low-power aspects

Digital system clocking high performance and low-power aspects

Digital system clocking high performance and low-power aspects

Author

Oklobdzija, Vojin G. John Wiley & Sons.

Preferred Shelf Number

ONLINE

Electronic Access

IEEE Xplore http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5224656

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9.

Cover image for Digital system clocking : high performance and low-power aspects

Digital system clocking : high performance and low-power aspects

Digital system clocking : high performance and low-power aspects

Author

Oklobdzija, Vojin G., ort. yaz.

Preferred Shelf Number

TK 7868.T5 D54 2003

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Beytepe Library~1

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10.

Cover image for Synchronization of digital telecommunications networks

Synchronization of digital telecommunications networks

Synchronization of digital telecommunications networks

Author

Bregni, Stefano.

Preferred Shelf Number

ONLINE

Electronic Access

Available by subscription from Safari Books Online
John Wiley http://dx.doi.org/10.1002/0470845880
HathiTrust Digital Library Limited view (search only) http://catalog.hathitrust.org/api/volumes/oclc/46600898.html
Volltext http://proquest.tech.safaribooksonline.de/9780471615507

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11.

Cover image for Skew-tolerant circuit design

Skew-tolerant circuit design

Skew-tolerant circuit design

Author

Harris, David Money.

Preferred Shelf Number

ONLINE

Electronic Access

ScienceDirect http://www.sciencedirect.com/science/book/9781558606364

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12.

Cover image for Monolithic phase-locked loops and clock recovery circuits theory and design

Monolithic phase-locked loops and clock recovery circuits theory and design

Monolithic phase-locked loops and clock recovery circuits theory and design

Author

Razavi, Behzad.

Preferred Shelf Number

ONLINE

Electronic Access

IEEE Xplore http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5263221

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Online Library~1

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1

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