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Cover image for Design of cost-efficient interconnect processing units : Spidergon STNoC
Design of cost-efficient interconnect processing units : Spidergon STNoC
Author 
Coppola, Marcello.
Preferred Shelf Number 
TK5105.546 .D47 2009
Electronic Access 
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2. 
Cover image for Multi-processor system-on-chip. 2, Applications
Multi-processor system-on-chip. 2, Applications
Author 
Andrade, Liliana, editor. Rousseau, Frédéric, 1967- editor.
Preferred Shelf Number 
TK7895 .E42
Electronic Access 
https://onlinelibrary.wiley.com/doi/book/10.1002/9781119818410
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