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Cover image for Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog
Title:
Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog
Author:
Taraate, Vaibbhav. author.
ISBN:
9789811087769
Edition:
1st ed. 2019.
Physical Description:
XXI, 307 p. 263 illus., 196 illus. in color. online resource.
Subject Term:
Electronic circuits.

Microprogramming .

Logic design.
Added Corporate Author:
SpringerLink (Online service)
Electronic Access:
https://doi.org/10.1007/978-981-10-8776-9
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