Cover image for Design of cost-efficient interconnect processing units : Spidergon STNoC
Title:
Design of cost-efficient interconnect processing units : Spidergon STNoC
Author:
Coppola, Marcello.
ISBN:
9781315219936

9781351827133
Physical Description:
1 online resource (xxi, 263 pages).
Series:
System-on-chip design and technologies

System-on-chip design and technologies.
Contents:
1. Towards multicores : technology and software complexity -- 2. On-chip bus vs. network-on-chip -- 3. NoC topology -- 4. The Spidergon STNoC -- 5. SoC and NoC design methodology and tools -- 6. Conclusions and future work -- References -- Index.
Corporate Subject:
Added Author:
Electronic Access:
Click here to view.
Holds:
Copies:

Available:*

Library
Material Type
Item Barcode
Shelf Number
Status
Item Holds
Searching...
E-Book 539486-1001 TK5105.546 .D47 2009
Searching...

On Order