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1. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers
Author 
Svensson, Lars. editor. Monteiro, José. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-3-540-95948-9
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Cover image for Language-driven Exploration and Implementation of Partially Re-configurable ASIPs
Language-driven Exploration and Implementation of Partially Re-configurable ASIPs
Author 
Chattopadhyay, Anupam. author. Leupers, Rainer. author. Meyr, Heinrich. author. Ascheid, Gerd. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-9297-8
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Cover image for Planar Double-Gate Transistor From Technology to Circuit
Planar Double-Gate Transistor From Technology to Circuit
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Amara, Amara. editor. Rozeau, Olivier. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-9341-8
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Cover image for Analog Circuit Design High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management
Analog Circuit Design High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management
Author 
Steyaert, Michiel. editor. Roermund, Arthur H. M. van. editor. Casier, Herman. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-8944-2
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5. 
Cover image for Hardware Software Co-Design of a Multimedia SOC Platform
Hardware Software Co-Design of a Multimedia SOC Platform
Author 
Chen, Sao-Jie. author. Lin, Guang-Huei. author. Hsiung, Pao-Ann. author. Hu, Yu-Hen. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-9623-5
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6. 
Cover image for Open Verification Methodology Cookbook
Open Verification Methodology Cookbook
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Glasser, Mark. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-0968-8
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7. 
Cover image for Languages for Embedded Systems and their Applications Selected Contributions on Specification, Design, and Verification from FDL’08
Languages for Embedded Systems and their Applications Selected Contributions on Specification, Design, and Verification from FDL’08
Author 
Radetzki, Martin. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-9714-0
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8. 
Cover image for Offset Reduction Techniques in Highspeed Analog-To-Digital Converters Analysis, Design and Tradeoffs
Offset Reduction Techniques in Highspeed Analog-To-Digital Converters Analysis, Design and Tradeoffs
Author 
Figueiredo, Pedro M. author. Vital, JoÃo C. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-9716-4
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9. 
Cover image for Designing Reliable and Efficient Networks on Chips
Designing Reliable and Efficient Networks on Chips
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Murali, Srinivasan. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-9757-7
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10. 
Cover image for Dynamic Offset Compensated CMOS Amplifiers
Dynamic Offset Compensated CMOS Amplifiers
Author 
Witte, Johan F. author. Makinwa, Kofi A. A. author. Huijsing, Johan H. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-90-481-2756-6
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11. 
Cover image for Test Pattern Generation using Boolean Proof Engines
Test Pattern Generation using Boolean Proof Engines
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Drechsler, Rolf. author. Eggersglüβ, Stephan. author. Fey, Görschwin. author. Tille, Daniel. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-90-481-2360-5
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12. 
Cover image for 1V CMOS Gm-C Filters Design and Applications
1V CMOS Gm-C Filters Design and Applications
Author 
Lo, Tien-Yu. editor. Hung, Chung-Chih. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-90-481-2410-7
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