System Verilog for Verification A Guide to Learning the Testbench Language Features

SAT-Based Scalable Formal Verification Solutions

Closing the Power Gap Between ASIC & Custom Tools and Techniques for Low Power Design

Verilog and SystemVerilog Gotchas 101 Common Coding Errors and How to Avoid Them

Writing Testbenches using System Verilog

Digital Design and Implementation with Field Programmable Devices

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings

Assertion-Based Design