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13. 
Cover image for Hardware Security Primitives
Hardware Security Primitives
Author 
Tehranipoor, Mark. author. Pundir, Nitin. author. Vashistha, Nidish. author. Farahmandi, Farimah. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-031-19185-5
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14. 
Cover image for Contemporary High Performance Computing : From Petascale toward Exascale
Contemporary High Performance Computing : From Petascale toward Exascale
Author 
Vetter, Jeffrey S., editor.
Preferred Shelf Number 
QA76.88 C668 2017
Electronic Access 
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15. 
Cover image for VLSI Design and Test 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers
VLSI Design and Test 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers
Author 
Kaushik, Brajesh Kumar. editor. Dasgupta, Sudeb. editor. Singh, Virendra. editor. (orcid)0000-0002-9113-5167 SpringerLink (Online service)
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https://doi.org/10.1007/978-981-10-7470-7
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16. 
Cover image for Emerging Technology and Architecture for Big-data Analytics
Emerging Technology and Architecture for Big-data Analytics
Author 
Chattopadhyay, Anupam. editor. (orcid)0000-0002-8818-6983 Chang, Chip Hong. editor. Yu, Hao. editor. SpringerLink (Online service)
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Electronic Access 
https://doi.org/10.1007/978-3-319-54840-1
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17. 
Cover image for Languages and Compilers for Parallel Computing 29th International Workshop, LCPC 2016, Rochester, NY, USA, September 28-30, 2016, Revised Papers
Languages and Compilers for Parallel Computing 29th International Workshop, LCPC 2016, Rochester, NY, USA, September 28-30, 2016, Revised Papers
Author 
Ding, Chen. editor. Criswell, John. editor. Wu, Peng. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-52709-3
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18. 
Cover image for Invasive Tightly Coupled Processor Arrays
Invasive Tightly Coupled Processor Arrays
Author 
LARI, VAHID. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-981-10-1058-3
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19. 
Cover image for IP Cores Design from Specifications to Production Modeling, Verification, Optimization, and Protection
IP Cores Design from Specifications to Production Modeling, Verification, Optimization, and Protection
Author 
Mohamed, Khaled Salah. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-22035-2
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20. 
Cover image for Heterogeneous Reconfigurable Processors for Real-Time Baseband Processing From Algorithm to Architecture
Heterogeneous Reconfigurable Processors for Real-Time Baseband Processing From Algorithm to Architecture
Author 
Zhang, Chenxin. author. Liu, Liang. author. Öwall, Viktor. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-24004-6
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21. 
Cover image for Spintronics-based Computing
Spintronics-based Computing
Author 
Zhao, Weisheng. editor. Prenat, Guillaume. editor. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-15180-9
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22. 
Cover image for Multi-core cache hierarchies
Multi-core cache hierarchies
Author 
Balasubramonian, Rajeev, 1977- Jouppi, Norman P. (Norman Paul) Muralimanohar, Naveen.
Preferred Shelf Number 
ONLINE
Electronic Access 
EBSCOhost http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=440440
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23. 
Cover image for Computer organization, design, and architecture
Computer organization, design, and architecture
Author 
Shiva, Sajjan G., author. Shiva, Sajjan G. Computer design and architecture.
Preferred Shelf Number 
TK7885 .S525 2008
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24. 
Cover image for Speculative execution in high-performance computer architectures
Speculative execution in high-performance computer architectures
Author 
Kaeli, David R. Yew, Pen-Chung, 1950-
Preferred Shelf Number 
QA76.9 .A73 K32 2005
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