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13. 
Cover image for From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators
From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators
Author 
Rahimi, Abbas. author. Benini, Luca. author. Gupta, Rajesh K. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-53768-9
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14. 
Cover image for Hardware IP Security and Trust
Hardware IP Security and Trust
Author 
Mishra, Prabhat. editor. Bhunia, Swarup. editor. Tehranipoor, Mark. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-49025-0
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15. 
Cover image for Fundamentals of Electronic Systems Design
Fundamentals of Electronic Systems Design
Author 
Lienig, Jens. author. (orcid)0000-0002-2140-4587 Bruemmer, Hans. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-55840-0
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16. 
Cover image for Designing with Xilinx® FPGAs Using Vivado
Designing with Xilinx® FPGAs Using Vivado
Author 
Churiwala, Sanjay. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-42438-5
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17. 
Cover image for Hardware Protection through Obfuscation
Hardware Protection through Obfuscation
Author 
Forte, Domenic. editor. Bhunia, Swarup. editor. Tehranipoor, Mark M. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-49019-9
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18. 
Cover image for Introduction to Logic Circuits & Logic Design with VHDL
Introduction to Logic Circuits & Logic Design with VHDL
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-34195-8
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19. 
Cover image for Fundamentals of Computer Architecture and Design
Fundamentals of Computer Architecture and Design
Author 
Bindal, Ahmet. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-25811-9
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20. 
Cover image for VLSI Design and Test 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers
VLSI Design and Test 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers
Author 
Kaushik, Brajesh Kumar. editor. Dasgupta, Sudeb. editor. Singh, Virendra. editor. (orcid)0000-0002-9113-5167 SpringerLink (Online service)
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https://doi.org/10.1007/978-981-10-7470-7
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21. 
Cover image for Introduction to Logic Circuits & Logic Design with Verilog
Introduction to Logic Circuits & Logic Design with Verilog
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-53883-9
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22. 
Cover image for Digital Systems From Logic Gates to Processors
Digital Systems From Logic Gates to Processors
Author 
Deschamps, Jean-Pierre. author. Valderrama, Elena. author. Terés, Lluís. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-41198-9
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23. 
Cover image for Operational Amplifiers Theory and Design
Operational Amplifiers Theory and Design
Author 
Huijsing, Johan. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-28127-8
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24. 
Cover image for Fundamentals of IP and SoC Security Design, Verification, and Debug
Fundamentals of IP and SoC Security Design, Verification, and Debug
Author 
Bhunia, Swarup. editor. Ray, Sandip. editor. Sur-Kolay, Susmita. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-50057-7
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