Limit Search Results
Author
SpringerLink (Online service)
(33)
LaMeres, Brock J. author.
(6)
Andrade, Diego. editor. (orcid)0000-0001-5670-7425
(2)
Caino-Lores, Silvina. editor. (orcid)0000-0002-6922-0138
(2)
Cucinotta, Tommaso. editor. (orcid)0000-0002-0362-0657
(2)
Language
Publication Date
-
Subject
Material Type
Shelf Location
Library
Switch to list view
Switch to thumbnail view
Select an Action
33 Results Found Subscribe to search results
000000000000DEFAULT
Print
13. 
Cover image for Analog Integrated Circuit Design Automation Placement, Routing and Parasitic Extraction Techniques
Analog Integrated Circuit Design Automation Placement, Routing and Parasitic Extraction Techniques
Author 
Martins, Ricardo. author. (orcid)0000-0002-8251-1415 Lourenço, Nuno. author. Horta, Nuno. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-34060-9
Format: 
Availability 
Online Library~1
Available:
Copies:
14. 
Cover image for Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
Author 
Lourenço, Nuno. author. Martins, Ricardo. author. (orcid)0000-0002-8251-1415 Horta, Nuno. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-42037-0
Format: 
Availability 
Online Library~1
Available:
Copies:
15. 
Cover image for Formal Verification of Simulink/Stateflow Diagrams A Deductive Approach
Formal Verification of Simulink/Stateflow Diagrams A Deductive Approach
Author 
Zhan, Naijun. author. Wang, Shuling. author. (orcid)0000-0002-2798-2660 Zhao, Hengjun. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-47016-0
Format: 
Availability 
Online Library~1
Available:
Copies:
16. 
Cover image for Hardware Security and Trust Design and Deployment of Integrated Circuits in a Threatened Environment
Hardware Security and Trust Design and Deployment of Integrated Circuits in a Threatened Environment
Author 
Sklavos, Nicolas. editor. Chaves, Ricardo. editor. Di Natale, Giorgio. editor. Regazzoni, Francesco. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-44318-8
Format: 
Availability 
Online Library~1
Available:
Copies:
17. 
Cover image for The Dark Side of Silicon Energy Efficient Computing in the Dark Silicon Era
The Dark Side of Silicon Energy Efficient Computing in the Dark Silicon Era
Author 
Rahmani, Amir M. editor. Liljeberg, Pasi. editor. Hemani, Ahmed. editor. Jantsch, Axel. editor. Tenhunen, Hannu. editor.
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-31596-6
Format: 
Availability 
Online Library~1
Available:
Copies:
18. 
Cover image for Introduction to Logic Circuits & Logic Design with VHDL
Introduction to Logic Circuits & Logic Design with VHDL
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-34195-8
Format: 
Availability 
Online Library~1
Available:
Copies:
19. 
Cover image for Handbook of Hardware/Software Codesign
Handbook of Hardware/Software Codesign
Author 
Ha, Soonhoi. editor. Teich, Jürgen. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-94-017-7267-9
Format: 
Availability 
Online Library~1
Available:
Copies:
20. 
Cover image for Scaling OpenMP for Exascale Performance and Portability 13th International Workshop on OpenMP, IWOMP 2017, Stony Brook, NY, USA, September 20-22, 2017, Proceedings
Scaling OpenMP for Exascale Performance and Portability 13th International Workshop on OpenMP, IWOMP 2017, Stony Brook, NY, USA, September 20-22, 2017, Proceedings
Author 
de Supinski, Bronis R. editor. Olivier, Stephen L. editor. Terboven, Christian. editor. Chapman, Barbara M. editor. Müller, Matthias S. editor.
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-65578-9
Format: 
Availability 
Online Library~1
Available:
Copies:
21. 
Cover image for Introduction to Logic Circuits & Logic Design with Verilog
Introduction to Logic Circuits & Logic Design with Verilog
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-53883-9
Format: 
Availability 
Online Library~1
Available:
Copies:
22. 
Cover image for Digital Systems From Logic Gates to Processors
Digital Systems From Logic Gates to Processors
Author 
Deschamps, Jean-Pierre. author. Valderrama, Elena. author. Terés, Lluís. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-41198-9
Format: 
Availability 
Online Library~1
Available:
Copies:
23. 
Cover image for New Data Structures and Algorithms for Logic Synthesis and Verification
New Data Structures and Algorithms for Logic Synthesis and Verification
Author 
Amaru, Luca Gaetano. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-43174-1
Format: 
Availability 
Online Library~1
Available:
Copies:
24. 
Cover image for Distributed Simulation A Model Driven Engineering Approach
Distributed Simulation A Model Driven Engineering Approach
Author 
Topçu, Okan. author. Durak, Umut. author. Oğuztüzün, Halit. author. Yilmaz, Levent. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-03050-0
Format: 
Availability 
Online Library~1
Available:
Copies: