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13. 
Cover image for On-chip High-Voltage Generator Design Design Methodology for Charge Pumps
On-chip High-Voltage Generator Design Design Methodology for Charge Pumps
Author 
Tanzawa, Toru. author. SpringerLink (Online service)
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Electronic Access 
https://doi.org/10.1007/978-3-319-21975-2
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14. 
Cover image for Crosstalk in Modern On-Chip Interconnects A FDTD Approach
Crosstalk in Modern On-Chip Interconnects A FDTD Approach
Author 
Kaushik, B.K. author. Kumar, V. Ramesh. author. Patnaik, Amalendu. author. SpringerLink (Online service)
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Electronic Access 
https://doi.org/10.1007/978-981-10-0800-9
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15. 
Cover image for Analysis and Design of Networks-on-Chip Under High Process Variation
Analysis and Design of Networks-on-Chip Under High Process Variation
Author 
Ezz-Eldin, Rabab. author. El-Moursy, Magdy Ali. author. Hamed, Hesham F. A. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-25766-2
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16. 
Cover image for On-Chip Electro-Static Discharge (ESD) Protection for Radio-Frequency Integrated Circuits
On-Chip Electro-Static Discharge (ESD) Protection for Radio-Frequency Integrated Circuits
Author 
Cui, Qiang. author. Liou, Juin J. author. Hajjar, Jean-Jacques. author. Salcedo, Javier. author. Zhou, Yuanzhong. author.
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https://doi.org/10.1007/978-3-319-10819-3
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17. 
Cover image for Microarchitecture of Network-on-Chip Routers A Designer's Perspective
Microarchitecture of Network-on-Chip Routers A Designer's Perspective
Author 
Dimitrakopoulos, Giorgos. author. Psarras, Anastasios. author. Seitanidis, Ioannis. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-1-4614-4301-8
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18. 
Cover image for Wafer-Level Chip-Scale Packaging Analog and Power Semiconductor Applications
Wafer-Level Chip-Scale Packaging Analog and Power Semiconductor Applications
Author 
Qu, Shichun. author. Liu, Yong. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-1-4939-1556-9
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19. 
Cover image for Designing 2D and 3D Network-on-Chip Architectures
Designing 2D and 3D Network-on-Chip Architectures
Author 
Tatas, Konstantinos. author. Siozios, Kostas. author. Soudris, Dimitrios. author. Jantsch, Axel. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-1-4614-4274-5
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20. 
Cover image for Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling
Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling
Author 
Mandal, Ayan. author. Khatri, Sunil P. author. Mahapatra, Rabi. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-1-4614-9405-8
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21. 
Cover image for Debugging Systems-on-Chip Communication-centric and Abstraction-based Techniques
Debugging Systems-on-Chip Communication-centric and Abstraction-based Techniques
Author 
Vermeulen, Bart. author. Goossens, Kees. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-06242-6
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22. 
Cover image for Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012
Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012
Author 
Haase, Jan. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-01418-0
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23. 
Cover image for Embedded Memory Design for Multi-Core and Systems on Chip
Embedded Memory Design for Multi-Core and Systems on Chip
Author 
Mohammad, Baker. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-1-4614-8881-1
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24. 
Cover image for Introduction to Open Core Protocol Fastpath to System-on-Chip Design
Introduction to Open Core Protocol Fastpath to System-on-Chip Design
Author 
Schwaderer, W David. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4614-0103-2
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