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13. 
Cover image for Microprocessor. 1, Prolegomena -- Calculation and storage functions -- Models of computation and computer architecture
Microprocessor. 1, Prolegomena -- Calculation and storage functions -- Models of computation and computer architecture
Author 
Darche, Philippe.
Preferred Shelf Number 
QA76.5 .D37 2020 EB
Electronic Access 
https://onlinelibrary.wiley.com/doi/book/10.1002/9781119779667
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14. 
Cover image for Microprocessor. 4, Core concepts -- software aspects
Microprocessor. 4, Core concepts -- software aspects
Author 
Darche, Philippe, author.
Preferred Shelf Number 
QA76.5
Electronic Access 
https://onlinelibrary.wiley.com/doi/book/10.1002/9781119801979
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15. 
Cover image for Computing Platforms for Software-Defined Radio
Computing Platforms for Software-Defined Radio
Author 
Hussain, Waqar. editor. Nurmi, Jari. editor. Isoaho, Jouni. editor. Garzia, Fabio. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-49679-5
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16. 
Cover image for Introduction to Logic Circuits & Logic Design with VHDL
Introduction to Logic Circuits & Logic Design with VHDL
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-34195-8
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17. 
Cover image for Introduction to Logic Circuits & Logic Design with Verilog
Introduction to Logic Circuits & Logic Design with Verilog
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-53883-9
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18. 
Cover image for Testing of Interposer-Based 2.5D Integrated Circuits
Testing of Interposer-Based 2.5D Integrated Circuits
Author 
Wang, Ran. author. Chakrabarty, Krishnendu. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-54714-5
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19. 
Cover image for Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
Author 
Lourenço, Nuno. author. Martins, Ricardo. author. (orcid)0000-0002-8251-1415 Horta, Nuno. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-42037-0
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20. 
Cover image for Designing with Xilinx® FPGAs Using Vivado
Designing with Xilinx® FPGAs Using Vivado
Author 
Churiwala, Sanjay. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-42438-5
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21. 
Cover image for FPGAs and Parallel Architectures for Aerospace Applications Soft Errors and Fault-Tolerant Design
FPGAs and Parallel Architectures for Aerospace Applications Soft Errors and Fault-Tolerant Design
Author 
Kastensmidt, Fernanda. editor. Rech, Paolo. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-14352-1
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22. 
Cover image for SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applications
SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applications
Author 
Mehta, Ashok B. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-30539-4
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23. 
Cover image for Design for Manufacturability with Advanced Lithography
Design for Manufacturability with Advanced Lithography
Author 
Yu, Bei. author. Pan, David Z. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-20385-0
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24. 
Cover image for Memory Controllers for Mixed-Time-Criticality Systems Architectures, Methodologies and Trade-offs
Memory Controllers for Mixed-Time-Criticality Systems Architectures, Methodologies and Trade-offs
Author 
Goossens, Sven. author. Chandrasekar, Karthik. author. Akesson, Benny. author. Goossens, Kees. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-32094-6
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