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25. 
Cover image for Introduction to Logic Circuits & Logic Design with VHDL
Introduction to Logic Circuits & Logic Design with VHDL
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-34195-8
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26. 
Cover image for Computer-Aided Design of Microfluidic Very Large Scale Integration (mVLSI) Biochips Design Automation, Testing, and Design-for-Testability
Computer-Aided Design of Microfluidic Very Large Scale Integration (mVLSI) Biochips Design Automation, Testing, and Design-for-Testability
Author 
Hu, Kai. author. Chakrabarty, Krishnendu. author. Ho, Tsung-Yi. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-56255-1
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27. 
Cover image for Hardware Protection through Obfuscation
Hardware Protection through Obfuscation
Author 
Forte, Domenic. editor. Bhunia, Swarup. editor. Tehranipoor, Mark M. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-49019-9
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28. 
Cover image for Carbon Nanotubes for Interconnects Process, Design and Applications
Carbon Nanotubes for Interconnects Process, Design and Applications
Author 
Todri-Sanial, Aida. editor. Dijon, Jean. editor. Maffucci, Antonio. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-29746-0
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29. 
Cover image for Hardware IP Security and Trust
Hardware IP Security and Trust
Author 
Mishra, Prabhat. editor. Bhunia, Swarup. editor. Tehranipoor, Mark. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-49025-0
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30. 
Cover image for Introduction to Logic Circuits & Logic Design with Verilog
Introduction to Logic Circuits & Logic Design with Verilog
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-53883-9
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31. 
Cover image for Fundamentals of Electronic Systems Design
Fundamentals of Electronic Systems Design
Author 
Lienig, Jens. author. (orcid)0000-0002-2140-4587 Bruemmer, Hans. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-55840-0
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32. 
Cover image for Hardware Security and Trust Design and Deployment of Integrated Circuits in a Threatened Environment
Hardware Security and Trust Design and Deployment of Integrated Circuits in a Threatened Environment
Author 
Sklavos, Nicolas. editor. Chaves, Ricardo. editor. Di Natale, Giorgio. editor. Regazzoni, Francesco. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-44318-8
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33. 
Cover image for Testing of Interposer-Based 2.5D Integrated Circuits
Testing of Interposer-Based 2.5D Integrated Circuits
Author 
Wang, Ran. author. Chakrabarty, Krishnendu. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-54714-5
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34. 
Cover image for VLSI Design and Test 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers
VLSI Design and Test 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers
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Kaushik, Brajesh Kumar. editor. Dasgupta, Sudeb. editor. Singh, Virendra. editor. (orcid)0000-0002-9113-5167 SpringerLink (Online service)
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https://doi.org/10.1007/978-981-10-7470-7
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35. 
Cover image for Parallel Sparse Direct Solver for Integrated Circuit Simulation
Parallel Sparse Direct Solver for Integrated Circuit Simulation
Author 
Chen, Xiaoming. author. Wang, Yu. author. Yang, Huazhong. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-53429-9
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36. 
Cover image for Foundations of Hardware IP Protection
Foundations of Hardware IP Protection
Author 
Bossuet, Lilian. editor. Torres, Lionel. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-50380-6
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