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Cover image for Technology evolution for silicon nano-electronics selected, peer reviewed papers from the proceedings of the International Symposium on Technology Evolution for Silicon Nano-Electronics 2010, June 3-5, 2010, Tokyo Institute of Technology, Tokyo, Japan
Technology evolution for silicon nano-electronics selected, peer reviewed papers from the proceedings of the International Symposium on Technology Evolution for Silicon Nano-Electronics 2010, June 3-5, 2010, Tokyo Institute of Technology, Tokyo, Japan
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International Symposium on Technology Evolution for Silicon Nano-Electronics (2010 : Tokyo Institute of Technology) Miyazaki, Seiichi. Tabata, Hitoshi.
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EBSCOhost http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=553066
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Cover image for CMOS analog circuit design
CMOS analog circuit design
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Allen, P. E. (Phillip E.) Holberg, Douglas R.
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ScienceDirect http://www.sciencedirect.com/science/book/9780123851857
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Cover image for CMOS Analog Design Using All-Region MOSFET Modeling
CMOS Analog Design Using All-Region MOSFET Modeling
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Schneider, Márcio Cherem. Galup-Montoro, Carlos.
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4. 
Cover image for CMOS circuit design, layout, and simulation
CMOS circuit design, layout, and simulation
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Baker, R. Jacob, 1964- Wiley InterScience (Online service)
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Wiley InterScience An electronic book accessible through the World Wide Web; click for information
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Cover image for Electronic device architectures for the nano-CMOS era from ultimate CMOS scaling to beyond CMOS devices
Electronic device architectures for the nano-CMOS era from ultimate CMOS scaling to beyond CMOS devices
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Deleonibus, Simon.
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Cover image for Reliability wearout mechanisms in advanced CMOS technologies
Reliability wearout mechanisms in advanced CMOS technologies
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Strong, Alvin Wayne, 1946-
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IEEE Xplore http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5361029
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Cover image for Transient-induced latchup in CMOS integrated circuits
Transient-induced latchup in CMOS integrated circuits
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Ker, Ming-Dou. Hsu, Sheng-Fu.
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IEEE Xplore http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5453758
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8. 
Cover image for Nano-CMOS design for manufacturability robust circuit and physical design for sub-65 nm technology nodes
Nano-CMOS design for manufacturability robust circuit and physical design for sub-65 nm technology nodes
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Wong, Ban P., 1953-
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Knovel http://app.knovel.com/web/toc.v/cid:kpNCMOSDM2
John Wiley http://dx.doi.org/10.1002/9780470382820
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9. 
Cover image for Wireless technologies circuits, systems, and devices
Wireless technologies circuits, systems, and devices
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Iniewski, Krzysztof.
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Cover image for Smart CMOS image sensors and applications
Smart CMOS image sensors and applications
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Ohta, Jun.
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Cover image for Tradeoffs and optimization in analog CMOS design
Tradeoffs and optimization in analog CMOS design
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Binkley, David M. Wiley InterScience (Online service)
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John Wiley http://dx.doi.org/10.1002/9780470033715
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12. 
Cover image for Fabrication of SiGe HBT BiCMOS technology
Fabrication of SiGe HBT BiCMOS technology
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Cressler, John D.
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