Limit Search Results
Author
SpringerLink (Online service)
(46)
LaMeres, Brock J. author.
(5)
Atmaca, Eren. author.
(2)
Bhunia, Swarup. editor.
(2)
Chattopadhyay, Anupam. editor. (orcid)0000-0002-8818-6983
(2)
Language
Publication Date
-
Subject
Material Type
Shelf Location
Library
Switch to list view
Switch to thumbnail view
Select an Action
46 Results Found Subscribe to search results
000000000000DEFAULT
Print
25. 
Cover image for Automatic Methods for the Refinement of System Models From the Specification to the Implementation
Automatic Methods for the Refinement of System Models From the Specification to the Implementation
Author 
Seiter, Julia. author. Wille, Robert. author. Drechsler, Rolf. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-41480-5
Format: 
Availability 
Online Library~1
Available:
Copies:
26. 
Cover image for Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
Author 
Lourenço, Nuno. author. Martins, Ricardo. author. (orcid)0000-0002-8251-1415 Horta, Nuno. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-42037-0
Format: 
Availability 
Online Library~1
Available:
Copies:
27. 
Cover image for Electromigration Inside Logic Cells Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS
Electromigration Inside Logic Cells Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS
Author 
Posser, Gracieli. author. Sapatnekar, Sachin S. author. Reis, Ricardo. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-48899-8
Format: 
Availability 
Online Library~1
Available:
Copies:
28. 
Cover image for Hardware IP Security and Trust
Hardware IP Security and Trust
Author 
Mishra, Prabhat. editor. Bhunia, Swarup. editor. Tehranipoor, Mark. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-49025-0
Format: 
Availability 
Online Library~1
Available:
Copies:
29. 
Cover image for Task Scheduling for Multi-core and Parallel Architectures Challenges, Solutions and Perspectives
Task Scheduling for Multi-core and Parallel Architectures Challenges, Solutions and Perspectives
Author 
Chen, Quan. author. Guo, Minyi. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-981-10-6238-4
Format: 
Availability 
Online Library~1
Available:
Copies:
30. 
Cover image for Formal Verification of Simulink/Stateflow Diagrams A Deductive Approach
Formal Verification of Simulink/Stateflow Diagrams A Deductive Approach
Author 
Zhan, Naijun. author. Wang, Shuling. author. (orcid)0000-0002-2798-2660 Zhao, Hengjun. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-47016-0
Format: 
Availability 
Online Library~1
Available:
Copies:
31. 
Cover image for Designing with Xilinx® FPGAs Using Vivado
Designing with Xilinx® FPGAs Using Vivado
Author 
Churiwala, Sanjay. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-42438-5
Format: 
Availability 
Online Library~1
Available:
Copies:
32. 
Cover image for Digital Systems From Logic Gates to Processors
Digital Systems From Logic Gates to Processors
Author 
Deschamps, Jean-Pierre. author. Valderrama, Elena. author. Terés, Lluís. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-41198-9
Format: 
Availability 
Online Library~1
Available:
Copies:
33. 
Cover image for Testing of Interposer-Based 2.5D Integrated Circuits
Testing of Interposer-Based 2.5D Integrated Circuits
Author 
Wang, Ran. author. Chakrabarty, Krishnendu. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-54714-5
Format: 
Availability 
Online Library~1
Available:
Copies:
34. 
Cover image for New Data Structures and Algorithms for Logic Synthesis and Verification
New Data Structures and Algorithms for Logic Synthesis and Verification
Author 
Amaru, Luca Gaetano. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-43174-1
Format: 
Availability 
Online Library~1
Available:
Copies:
35. 
Cover image for Techniques for Building Timing-Predictable Embedded Systems
Techniques for Building Timing-Predictable Embedded Systems
Author 
Guan, Nan. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-27198-9
Format: 
Availability 
Online Library~1
Available:
Copies:
36. 
Cover image for 3D Stacked Chips From Emerging Processes to Heterogeneous Systems
3D Stacked Chips From Emerging Processes to Heterogeneous Systems
Author 
Elfadel, Ibrahim (Abe) M. editor. (orcid)0000-0003-3220-9987 Fettweis, Gerhard. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-20481-9
Format: 
Availability 
Online Library~1
Available:
Copies:
Select an Action