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25. 
Cover image for Analog Integrated Circuit Design Automation Placement, Routing and Parasitic Extraction Techniques
Analog Integrated Circuit Design Automation Placement, Routing and Parasitic Extraction Techniques
Author 
Martins, Ricardo. author. (orcid)0000-0002-8251-1415 Lourenço, Nuno. author. Horta, Nuno. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-34060-9
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26. 
Cover image for Designing with Xilinx® FPGAs Using Vivado
Designing with Xilinx® FPGAs Using Vivado
Author 
Churiwala, Sanjay. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-42438-5
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27. 
Cover image for New Data Structures and Algorithms for Logic Synthesis and Verification
New Data Structures and Algorithms for Logic Synthesis and Verification
Author 
Amaru, Luca Gaetano. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-43174-1
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28. 
Cover image for The Dark Side of Silicon Energy Efficient Computing in the Dark Silicon Era
The Dark Side of Silicon Energy Efficient Computing in the Dark Silicon Era
Author 
Rahmani, Amir M. editor. Liljeberg, Pasi. editor. Hemani, Ahmed. editor. Jantsch, Axel. editor. Tenhunen, Hannu. editor.
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https://doi.org/10.1007/978-3-319-31596-6
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29. 
Cover image for Introduction to Logic Circuits & Logic Design with VHDL
Introduction to Logic Circuits & Logic Design with VHDL
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-34195-8
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30. 
Cover image for Task Scheduling for Multi-core and Parallel Architectures Challenges, Solutions and Perspectives
Task Scheduling for Multi-core and Parallel Architectures Challenges, Solutions and Perspectives
Author 
Chen, Quan. author. Guo, Minyi. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-981-10-6238-4
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31. 
Cover image for Hardware IP Security and Trust
Hardware IP Security and Trust
Author 
Mishra, Prabhat. editor. Bhunia, Swarup. editor. Tehranipoor, Mark. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-49025-0
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32. 
Cover image for Introduction to Logic Circuits & Logic Design with Verilog
Introduction to Logic Circuits & Logic Design with Verilog
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-53883-9
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33. 
Cover image for Foundations of Hardware IP Protection
Foundations of Hardware IP Protection
Author 
Bossuet, Lilian. editor. Torres, Lionel. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-50380-6
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34. 
Cover image for Techniques for Building Timing-Predictable Embedded Systems
Techniques for Building Timing-Predictable Embedded Systems
Author 
Guan, Nan. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-27198-9
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35. 
Cover image for SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applications
SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applications
Author 
Mehta, Ashok B. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-30539-4
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36. 
Cover image for 3D Stacked Chips From Emerging Processes to Heterogeneous Systems
3D Stacked Chips From Emerging Processes to Heterogeneous Systems
Author 
Elfadel, Ibrahim (Abe) M. editor. (orcid)0000-0003-3220-9987 Fettweis, Gerhard. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-20481-9
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