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25. 
Cover image for Power Electronics and Instrumentation Engineering International Conference, PEIE 2010, Kochi, Kerala, India, September 7-9, 2010. Proceedings
Power Electronics and Instrumentation Engineering International Conference, PEIE 2010, Kochi, Kerala, India, September 7-9, 2010. Proceedings
Author 
Das, Vinu V. editor. Stephen, Janahanlal. editor. Thankachan, Nessy. editor. SpringerLink (Online service)
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Electronic Access 
http://dx.doi.org/10.1007/978-3-642-15739-4
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26. 
Cover image for Post-Silicon and Runtime Verification for Modern Processors
Post-Silicon and Runtime Verification for Modern Processors
Author 
Wagner, Ilya. author. Bertacco, Valeria. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-8034-2
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27. 
Cover image for Introduction to digital systems modeling, synthesis, and simulation using VHDL
Introduction to digital systems modeling, synthesis, and simulation using VHDL
Author 
Ferdjallah, Mohammed.
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EBSCOhost http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=382054
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28. 
Cover image for Design for embedded image processing on FPGAs
Design for embedded image processing on FPGAs
Author 
Bailey, Donald G. (Donald Graeme), 1962-
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IEEE Xplore http://ieeexplore.ieee.org/servlet/opac?bknumber=6016259
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29. 
Cover image for Advanced digital design with the Verilog HDL
Advanced digital design with the Verilog HDL
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Ciletti, Michael D.
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TK7885.7 C5485 2011
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30. 
Cover image for Verilog digital system design RT level synthesis, testbench, and verification
Verilog digital system design RT level synthesis, testbench, and verification
Author 
Navabi, Zainalabedin.
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31. 
Cover image for VHDL modular design and synthesis of cores and systems
VHDL modular design and synthesis of cores and systems
Author 
Navabi, Zainalabedin.
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32. 
Cover image for Embedded SOPC design with NIOS II processor and VHDL examples
Embedded SOPC design with NIOS II processor and VHDL examples
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Chu, Pong P., 1959- Wiley InterScience (Online service)
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Wiley InterScience An electronic book accessible through the World Wide Web; click for information
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http://site.ebrary.com/lib/alltitles/Doc?id=10560671
ebrary http://site.ebrary.com/id/10560671
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33. 
Cover image for National electrical safety code handbook a discussion of the National Safety Code Grounding Rules, and parts 1, 2, 3, and 4 of the 3rd (1920) through 2007 editions of the National Electrical Safety Code, American National Standard C2
National electrical safety code handbook a discussion of the National Safety Code Grounding Rules, and parts 1, 2, 3, and 4 of the 3rd (1920) through 2007 editions of the National Electrical Safety Code, American National Standard C2
Author 
Clapp, Allen L. American National Standards Institute. National Electrical Safety Code Committee. Institute of Electrical and Electronics Engineers.
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IEEE Xplore http://ieeexplore.ieee.org/servlet/opac?bknumber=5988886
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34. 
Cover image for VHDL for logic synthesis
VHDL for logic synthesis
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Rushton, Andrew.
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Books24x7 http://www.books24x7.com/marc.asp?bookid=41715
John Wiley http://dx.doi.org/10.1002/9781119995852
http://proquest.safaribooksonline.com/?fpi=9780470688472
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35. 
Cover image for Digital design, with RTL design, VHDL, and Verilog
Digital design, with RTL design, VHDL, and Verilog
Author 
Vahid, Frank.
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TK7888.3 V34 2011
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36. 
Cover image for Performance tuning of scientific applications
Performance tuning of scientific applications
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Bailey, David H. Lucas, Robert F. Williams, Samuel Watkins.
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Q183.9 .P47 2011
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