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1. 
Cover image for Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog
Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog
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Taraate, Vaibbhav. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-981-10-8776-9
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Cover image for Variant Construction from Theoretical Foundation to Applications
Variant Construction from Theoretical Foundation to Applications
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Zheng, Jeffrey. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-981-13-2282-2
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3. 
Cover image for High-Performance Modelling and Simulation for Big Data Applications Selected Results of the COST Action IC1406 cHiPSet
High-Performance Modelling and Simulation for Big Data Applications Selected Results of the COST Action IC1406 cHiPSet
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Kołodziej, Joanna. editor. (orcid)0000-0002-5181-8713 González-Vélez, Horacio. editor. (orcid)0000-0003-0241-6053 SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-16272-6
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4. 
Cover image for Transactions on Large-Scale Data- and Knowledge-Centered Systems XLII
Transactions on Large-Scale Data- and Knowledge-Centered Systems XLII
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Hameurlain, Abdelkader. editor. Wagner, Roland. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-662-60531-8
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5. 
Cover image for Quick Start Guide to VHDL
Quick Start Guide to VHDL
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LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-04516-6
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6. 
Cover image for Accelerator Programming Using Directives 5th International Workshop, WACCPD 2018, Dallas, TX, USA, November 11-17, 2018, Proceedings
Accelerator Programming Using Directives 5th International Workshop, WACCPD 2018, Dallas, TX, USA, November 11-17, 2018, Proceedings
Author 
Chandrasekaran, Sunita. editor. (orcid)0000-0002-3560-9428 Juckeland, Guido. editor. (orcid)0000-0002-9935-4428 Wienke, Sandra. editor. (orcid)0000-0002-5794-3662 SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-12274-4
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7. 
Cover image for Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms A Cross-layer Approach
Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms A Cross-layer Approach
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Fornaciari, William. editor. Soudris, Dimitrios. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-91962-1
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8. 
Cover image for Fundamentals of Modern Electric Circuit Analysis and Filter Synthesis A Transfer Function Approach
Fundamentals of Modern Electric Circuit Analysis and Filter Synthesis A Transfer Function Approach
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Izadian, Afshin. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-02484-0
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9. 
Cover image for Transactions on High-Performance Embedded Architectures and Compilers V
Transactions on High-Performance Embedded Architectures and Compilers V
Author 
Silvano, Cristina. editor. (orcid)0000-0003-1668-0883 Bertels, Koen. editor. (orcid)0000-0001-9310-4885 Schulte, Michael. editor. (orcid)0000-0002-0213-4155 SpringerLink (Online service)
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https://doi.org/10.1007/978-3-662-58834-5
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10. 
Cover image for Quick Start Guide to Verilog
Quick Start Guide to Verilog
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-10552-5
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11. 
Cover image for Supercomputing 4th Russian Supercomputing Days, RuSCDays 2018, Moscow, Russia, September 24–25, 2018, Revised Selected Papers
Supercomputing 4th Russian Supercomputing Days, RuSCDays 2018, Moscow, Russia, September 24–25, 2018, Revised Selected Papers
Author 
Voevodin, Vladimir. editor. (orcid)0000-0001-6036-5106 Sobolev, Sergey. editor. (orcid)0000-0002-3474-8696 SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-05807-4
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12. 
Cover image for Software Architecture 13th European Conference, ECSA 2019, Paris, France, September 9–13, 2019, Proceedings
Software Architecture 13th European Conference, ECSA 2019, Paris, France, September 9–13, 2019, Proceedings
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Bures, Tomas. editor. Duchien, Laurence. editor. (orcid)0000-0002-4517-5862 Inverardi, Paola. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-29983-5
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