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25. 
Cover image for Digital Systems From Logic Gates to Processors
Digital Systems From Logic Gates to Processors
Author 
Deschamps, Jean-Pierre. author. Valderrama, Elena. author. Terés, Lluís. author. SpringerLink (Online service)
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ONLINE
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https://doi.org/10.1007/978-3-319-41198-9
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26. 
Cover image for Testing of Interposer-Based 2.5D Integrated Circuits
Testing of Interposer-Based 2.5D Integrated Circuits
Author 
Wang, Ran. author. Chakrabarty, Krishnendu. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-54714-5
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27. 
Cover image for From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators
From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators
Author 
Rahimi, Abbas. author. Benini, Luca. author. Gupta, Rajesh K. author. SpringerLink (Online service)
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ONLINE
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https://doi.org/10.1007/978-3-319-53768-9
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28. 
Cover image for Analog Integrated Circuit Design Automation Placement, Routing and Parasitic Extraction Techniques
Analog Integrated Circuit Design Automation Placement, Routing and Parasitic Extraction Techniques
Author 
Martins, Ricardo. author. (orcid)0000-0002-8251-1415 Lourenço, Nuno. author. Horta, Nuno. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-34060-9
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29. 
Cover image for RFID Security A Lightweight Paradigm
RFID Security A Lightweight Paradigm
Author 
Khattab, Ahmed. author. Jeddi, Zahra. author. Amini, Esmaeil. author. Bayoumi, Magdy. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-47545-5
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30. 
Cover image for Emerging Technology and Architecture for Big-data Analytics
Emerging Technology and Architecture for Big-data Analytics
Author 
Chattopadhyay, Anupam. editor. (orcid)0000-0002-8818-6983 Chang, Chip Hong. editor. Yu, Hao. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-54840-1
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31. 
Cover image for Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
Author 
Lourenço, Nuno. author. Martins, Ricardo. author. (orcid)0000-0002-8251-1415 Horta, Nuno. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-42037-0
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32. 
Cover image for Designing with Xilinx® FPGAs Using Vivado
Designing with Xilinx® FPGAs Using Vivado
Author 
Churiwala, Sanjay. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-42438-5
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33. 
Cover image for New Data Structures and Algorithms for Logic Synthesis and Verification
New Data Structures and Algorithms for Logic Synthesis and Verification
Author 
Amaru, Luca Gaetano. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-43174-1
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34. 
Cover image for FPGAs and Parallel Architectures for Aerospace Applications Soft Errors and Fault-Tolerant Design
FPGAs and Parallel Architectures for Aerospace Applications Soft Errors and Fault-Tolerant Design
Author 
Kastensmidt, Fernanda. editor. Rech, Paolo. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-14352-1
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35. 
Cover image for SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applications
SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applications
Author 
Mehta, Ashok B. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-30539-4
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36. 
Cover image for 3D Stacked Chips From Emerging Processes to Heterogeneous Systems
3D Stacked Chips From Emerging Processes to Heterogeneous Systems
Author 
Elfadel, Ibrahim (Abe) M. editor. (orcid)0000-0003-3220-9987 Fettweis, Gerhard. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-20481-9
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