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1. 
Cover image for Scenarios: Models, Transformations and Tools International Workshop, Dagstuhl Castle, Germany, September 7-12, 2003, Revised Selected Papers
Scenarios: Models, Transformations and Tools International Workshop, Dagstuhl Castle, Germany, September 7-12, 2003, Revised Selected Papers
Author 
Leue, Stefan. editor. Systä, Tarja Johanna. editor. SpringerLink (Online service)
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Electronic Access 
http://dx.doi.org/10.1007/b137052
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2. 
Cover image for Analogue-digital ASICs Circuit techniques, design tools and applications
Analogue-digital ASICs Circuit techniques, design tools and applications
Author 
Soin, R. S., ed. Maloberti, F., ed. Franca, J., ed.
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http://dx.doi.org/10.1049/PBCS003E
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3. 
Cover image for Quick Start Guide to Verilog
Quick Start Guide to Verilog
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-44104-2
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4. 
Cover image for Introduction to Logic Circuits & Logic Design with Verilog
Introduction to Logic Circuits & Logic Design with Verilog
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-43946-9
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5. 
Cover image for Quick Start Guide to VHDL
Quick Start Guide to VHDL
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-42543-1
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6. 
Cover image for Introduction to Logic Circuits & Logic Design with VHDL
Introduction to Logic Circuits & Logic Design with VHDL
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-42547-9
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7. 
Cover image for Scaling OpenMP for Exascale Performance and Portability 13th International Workshop on OpenMP, IWOMP 2017, Stony Brook, NY, USA, September 20-22, 2017, Proceedings
Scaling OpenMP for Exascale Performance and Portability 13th International Workshop on OpenMP, IWOMP 2017, Stony Brook, NY, USA, September 20-22, 2017, Proceedings
Author 
de Supinski, Bronis R. editor. Olivier, Stephen L. editor. Terboven, Christian. editor. Chapman, Barbara M. editor. Müller, Matthias S. editor.
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https://doi.org/10.1007/978-3-319-65578-9
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8. 
Cover image for Introduction to Logic Circuits & Logic Design with VHDL
Introduction to Logic Circuits & Logic Design with VHDL
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-34195-8
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9. 
Cover image for New Data Structures and Algorithms for Logic Synthesis and Verification
New Data Structures and Algorithms for Logic Synthesis and Verification
Author 
Amaru, Luca Gaetano. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-43174-1
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10. 
Cover image for Introduction to Logic Circuits & Logic Design with Verilog
Introduction to Logic Circuits & Logic Design with Verilog
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-53883-9
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11. 
Cover image for Separation Logic for High-level Synthesis
Separation Logic for High-level Synthesis
Author 
Winterstein, Felix. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-53222-6
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