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1. 
Cover image for The Simple Art of SoC Design Closing the Gap between RTL and ESL
The Simple Art of SoC Design Closing the Gap between RTL and ESL
Author 
Keating, Michael. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-8586-6
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2. 
Cover image for Multi-objective Design Space Exploration of Multiprocessor SoC Architectures The MULTICUBE Approach
Multi-objective Design Space Exploration of Multiprocessor SoC Architectures The MULTICUBE Approach
Author 
Silvano, Cristina. editor. Fornaciari, William. editor. Villar, Eugenio. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-8837-9
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3. 
Cover image for Nano-Electronic Devices Semiclassical and Quantum Transport Modeling
Nano-Electronic Devices Semiclassical and Quantum Transport Modeling
Author 
Vasileska, Dragica. editor. Goodnick, Stephen M. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-8840-9
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4. 
Cover image for Principles of VLSI RTL Design A Practical Guide
Principles of VLSI RTL Design A Practical Guide
Author 
Churiwala, Sanjay. author. Garg, Sapan. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-9296-3
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5. 
Cover image for High-Level Verification Methods and Tools for Verification of System-Level Designs
High-Level Verification Methods and Tools for Verification of System-Level Designs
Author 
Kundu, Sudipta. author. Lerner, Sorin. author. Gupta, Rajesh K. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-9359-5
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6. 
Cover image for Reliability of Nanoscale Circuits and Systems Methodologies and Circuit Architectures
Reliability of Nanoscale Circuits and Systems Methodologies and Circuit Architectures
Author 
Stanisavljević, Miloš. author. Schmid, Alexandre. author. Leblebici, Yusuf. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-6217-1
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7. 
Cover image for Multiprocessor System-on-Chip Hardware Design and Tool Integration
Multiprocessor System-on-Chip Hardware Design and Tool Integration
Author 
Hübner, Michael. editor. Becker, Jürgen. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-6460-1
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8. 
Cover image for Focal-Plane Sensor-Processor Chips
Focal-Plane Sensor-Processor Chips
Author 
Zarándy, Ákos. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-6475-5
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9. 
Cover image for On-Chip Interconnect with aelite Composable and Predictable Systems
On-Chip Interconnect with aelite Composable and Predictable Systems
Author 
Hansson, Andreas. author. Goossens, Kees. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-6865-4
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10. 
Cover image for Low Power Networks-on-Chip
Low Power Networks-on-Chip
Author 
Silvano, Cristina. editor. Lajolo, Marcello. editor. Palermo, Gianluca. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-6911-8
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11. 
Cover image for Nanoscale Memory Repair
Nanoscale Memory Repair
Author 
Horiguchi, Masashi. author. Itoh, Kiyoo. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-7958-2
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12. 
Cover image for Post-Silicon and Runtime Verification for Modern Processors
Post-Silicon and Runtime Verification for Modern Processors
Author 
Wagner, Ilya. author. Bertacco, Valeria. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-8034-2
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