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37. 
Cover image for Fundamentals of Electromigration-Aware Integrated Circuit Design
Fundamentals of Electromigration-Aware Integrated Circuit Design
Author 
Lienig, Jens. author. (orcid)0000-0002-2140-4587 Rothe, Susann. author. Thiele, Matthias. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-80023-8
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38. 
Cover image for Integrated Circuit Design Tape-out Process with Open-Source Tools
Integrated Circuit Design Tape-out Process with Open-Source Tools
Author 
Ortega Cisneros, Susana. author. Baungarten Leon, Emilio Isaac. author. (orcid)0000-0001-6243-219X Mejia Alvarez, Pedro. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-92108-7
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39. 
Cover image for Euro-Par 2024: Parallel Processing Workshops Euro-Par 2024 International Workshops, Madrid, Spain, August 26-30, 2024, Proceedings, Part II
Euro-Par 2024: Parallel Processing Workshops Euro-Par 2024 International Workshops, Madrid, Spain, August 26-30, 2024, Proceedings, Part II
Author 
Caino-Lores, Silvina. editor. (orcid)0000-0002-6922-0138 Zeinalipour, Demetris. editor. (orcid)0000-0002-7239-2387 Doudali, Thaleia Dimitra. editor. (orcid)0000-0002-3197-839X Singh, David E. editor. (orcid)0000-0002-8125-0049 Garzón, Gracia Ester Martín. editor. (orcid)0000-0002-0568-5470
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https://doi.org/10.1007/978-3-031-90203-1
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40. 
Cover image for Space system architecture analysis and wargaming
Space system architecture analysis and wargaming
Author 
Rainey, Larry B., editor.
Preferred Shelf Number 
UG1530
Electronic Access 
Taylor & Francis https://www.taylorfrancis.com/books/9781003321811
OCLC metadata license agreement http://www.oclc.org/content/dam/oclc/forms/terms/vbrl-201703.pdf
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41. 
Cover image for Domain-Specific Computer Architectures for Emerging Applications : Machine Learning and Neural Networks
Domain-Specific Computer Architectures for Emerging Applications : Machine Learning and Neural Networks
Author 
Wang, Chao (Computer scientist), author.
Preferred Shelf Number 
QA76.9 .A73
Electronic Access 
Taylor & Francis https://www.taylorfrancis.com/books/9780429355080
OCLC metadata license agreement http://www.oclc.org/content/dam/oclc/forms/terms/vbrl-201703.pdf
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42. 
Cover image for Towards Heterogeneous Multi-core Systems-on-Chip for Edge Machine Learning Journey from Single-core Acceleration to Multi-core Heterogeneous Systems
Towards Heterogeneous Multi-core Systems-on-Chip for Edge Machine Learning Journey from Single-core Acceleration to Multi-core Heterogeneous Systems
Author 
Jain, Vikram. author. (orcid)0000-0002-1267-1683 Verhelst, Marian. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-38230-7
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43. 
Cover image for In-Memory Computing Hardware Accelerators for Data-Intensive Applications
In-Memory Computing Hardware Accelerators for Data-Intensive Applications
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Mohammad, Baker. editor. (orcid)0000-0002-6063-473X Halawani, Yasmin. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-34233-2
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44. 
Cover image for Introduction to Logic Circuits & Logic Design with Verilog
Introduction to Logic Circuits & Logic Design with Verilog
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-43946-9
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45. 
Cover image for Quick Start Guide to VHDL
Quick Start Guide to VHDL
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-42543-1
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46. 
Cover image for Introduction to Logic Circuits & Logic Design with VHDL
Introduction to Logic Circuits & Logic Design with VHDL
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-42547-9
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47. 
Cover image for High Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture
High Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture
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Yue, Jinshan. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-981-97-3477-1
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48. 
Cover image for Euro-Par 2024: Parallel Processing 30th European Conference on Parallel and Distributed Processing, Madrid, Spain, August 26-30, 2024, Proceedings, Part I
Euro-Par 2024: Parallel Processing 30th European Conference on Parallel and Distributed Processing, Madrid, Spain, August 26-30, 2024, Proceedings, Part I
Author 
Carretero, Jesus. editor. (orcid)0000-0002-1413-4793 Shende, Sameer. editor. (orcid)0000-0002-2592-669X Garcia-Blas, Javier. editor. (orcid)0000-0003-1452-1918 Brandic, Ivona. editor. (orcid)0000-0001-7424-0208 Olcoz, Katzalin. editor. (orcid)0000-0002-1821-124X
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https://doi.org/10.1007/978-3-031-69577-3
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