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Cover image for Global Product Development Proceedings of the 20th CIRP Design Conference, Ecole Centrale de Nantes, Nantes, France, 19th-21st April 2010
Global Product Development Proceedings of the 20th CIRP Design Conference, Ecole Centrale de Nantes, Nantes, France, 19th-21st April 2010
Author 
Bernard, Alain. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-3-642-15973-2
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Cover image for Cartesian Genetic Programming
Cartesian Genetic Programming
Author 
Miller, Julian F. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-3-642-17310-3
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Cover image for Complexity Metrics in Engineering Design Managing the Structure of Design Processes
Complexity Metrics in Engineering Design Managing the Structure of Design Processes
Author 
Kreimeyer, Matthias. author. Lindemann, Udo. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-3-642-20963-5
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4. 
Cover image for Building Innovation Pipelines through Computer-Aided Innovation 4th IFIP WG 5.4 Working Conference, CAI 2011, Strasbourg, France, June 30 – July 1, 2011. Proceedings
Building Innovation Pipelines through Computer-Aided Innovation 4th IFIP WG 5.4 Working Conference, CAI 2011, Strasbourg, France, June 30 – July 1, 2011. Proceedings
Author 
Cavallucci, Denis. editor. Guio, Roland. editor. Cascini, Gaetano. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-3-642-22182-8
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5. 
Cover image for Ontologies in Urban Development Projects
Ontologies in Urban Development Projects
Author 
Falquet, Gilles. author. Métral, Claudine. author. Teller, Jacques. author. Tweed, Christopher. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-85729-724-2
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6. 
Cover image for Multiprocessor System-on-Chip Hardware Design and Tool Integration
Multiprocessor System-on-Chip Hardware Design and Tool Integration
Author 
Hübner, Michael. editor. Becker, Jürgen. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-6460-1
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Cover image for Focal-Plane Sensor-Processor Chips
Focal-Plane Sensor-Processor Chips
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Zarándy, Ákos. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-6475-5
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Cover image for On-Chip Interconnect with aelite Composable and Predictable Systems
On-Chip Interconnect with aelite Composable and Predictable Systems
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Hansson, Andreas. author. Goossens, Kees. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-6865-4
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9. 
Cover image for Low Power Networks-on-Chip
Low Power Networks-on-Chip
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Silvano, Cristina. editor. Lajolo, Marcello. editor. Palermo, Gianluca. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-6911-8
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10. 
Cover image for Analog Layout Synthesis A Survey of Topological Approaches
Analog Layout Synthesis A Survey of Topological Approaches
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Graeb, Helmut E. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-6932-3
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11. 
Cover image for Nanoscale Memory Repair
Nanoscale Memory Repair
Author 
Horiguchi, Masashi. author. Itoh, Kiyoo. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-7958-2
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12. 
Cover image for Post-Silicon and Runtime Verification for Modern Processors
Post-Silicon and Runtime Verification for Modern Processors
Author 
Wagner, Ilya. author. Bertacco, Valeria. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-8034-2
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