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Cover image for VLSI Design and Test 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers
VLSI Design and Test 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers
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Kaushik, Brajesh Kumar. editor. Dasgupta, Sudeb. editor. Singh, Virendra. editor. (orcid)0000-0002-9113-5167 SpringerLink (Online service)
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https://doi.org/10.1007/978-981-10-7470-7
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Cover image for Embedded Software Verification and Debugging
Embedded Software Verification and Debugging
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Lettnin, Djones. editor. Winterholer, Markus. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-1-4614-2266-2
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Cover image for Introduction to Logic Circuits & Logic Design with VHDL
Introduction to Logic Circuits & Logic Design with VHDL
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LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-34195-8
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Cover image for High Performance Computing 32nd International Conference, ISC High Performance 2017, Frankfurt, Germany, June 18-22, 2017, Proceedings
High Performance Computing 32nd International Conference, ISC High Performance 2017, Frankfurt, Germany, June 18-22, 2017, Proceedings
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Kunkel, Julian M. editor. Yokota, Rio. editor. Balaji, Pavan. editor. Keyes, David. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-58667-0
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Cover image for Fundamentals of IP and SoC Security Design, Verification, and Debug
Fundamentals of IP and SoC Security Design, Verification, and Debug
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Bhunia, Swarup. editor. Ray, Sandip. editor. Sur-Kolay, Susmita. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-50057-7
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Cover image for Computing Platforms for Software-Defined Radio
Computing Platforms for Software-Defined Radio
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Hussain, Waqar. editor. Nurmi, Jari. editor. Isoaho, Jouni. editor. Garzia, Fabio. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-49679-5
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Cover image for Introduction to Logic Circuits & Logic Design with Verilog
Introduction to Logic Circuits & Logic Design with Verilog
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LaMeres, Brock J. author. SpringerLink (Online service)
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Cover image for Digital Systems From Logic Gates to Processors
Digital Systems From Logic Gates to Processors
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Deschamps, Jean-Pierre. author. Valderrama, Elena. author. Terés, Lluís. author. SpringerLink (Online service)
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Cover image for Languages, Design Methods, and Tools for Electronic System Design Selected Contributions from FDL 2015
Languages, Design Methods, and Tools for Electronic System Design Selected Contributions from FDL 2015
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Drechsler, Rolf. editor. Wille, Robert. editor. SpringerLink (Online service)
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Cover image for Invasive Tightly Coupled Processor Arrays
Invasive Tightly Coupled Processor Arrays
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LARI, VAHID. author. SpringerLink (Online service)
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Cover image for OpenMP: Memory, Devices, and Tasks 12th International Workshop on OpenMP, IWOMP 2016, Nara, Japan, October 5-7, 2016, Proceedings
OpenMP: Memory, Devices, and Tasks 12th International Workshop on OpenMP, IWOMP 2016, Nara, Japan, October 5-7, 2016, Proceedings
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Maruyama, Naoya. editor. de Supinski, Bronis R. editor. Wahib, Mohamed. editor. SpringerLink (Online service)
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12. 
Cover image for Smart Systems Integration and Simulation
Smart Systems Integration and Simulation
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Bombieri, Nicola. editor. Poncino, Massimo. editor. Pravadelli, Graziano. editor. (orcid)0000-0002-7833-1673 SpringerLink (Online service)
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