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49. 
Cover image for Correct-by-Construction Approaches for SoC Design
Correct-by-Construction Approaches for SoC Design
Author 
Sinha, Roopak. author. Roop, Parthasarathi. author. Basu, Samik. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-1-4614-7864-5
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50. 
Cover image for Routing Algorithms in Networks-on-Chip
Routing Algorithms in Networks-on-Chip
Author 
Palesi, Maurizio. editor. Daneshtalab, Masoud. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-1-4614-8274-1
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51. 
Cover image for Architectures for Baseband Signal Processing
Architectures for Baseband Signal Processing
Author 
Kienle, Frank. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-1-4614-8030-3
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52. 
Cover image for Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling
Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling
Author 
Mandal, Ayan. author. Khatri, Sunil P. author. Mahapatra, Rabi. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-1-4614-9405-8
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53. 
Cover image for Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
Author 
Noia, Brandon. author. Chakrabarty, Krishnendu. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-02378-6
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54. 
Cover image for Smart Multicore Embedded Systems
Smart Multicore Embedded Systems
Author 
Torquati, Massimo. editor. (orcid)0000-0001-6323-3459 Bertels, Koen. editor. Karlsson, Sven. editor. Pacull, François. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-1-4614-8800-2
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55. 
Cover image for Programming Heterogeneous MPSoCs Tool Flows to Close the Software Productivity Gap
Programming Heterogeneous MPSoCs Tool Flows to Close the Software Productivity Gap
Author 
Castrillón Mazo, Jerónimo. author. Leupers, Rainer. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-00675-8
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56. 
Cover image for High-Performance Computing on the Intel® Xeon Phi™ How to Fully Exploit MIC Architectures
High-Performance Computing on the Intel® Xeon Phi™ How to Fully Exploit MIC Architectures
Author 
Wang, Endong. author. Zhang, Qing. author. Shen, Bo. author. Zhang, Guangyong. author. Lu, Xiaowei. author.
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https://doi.org/10.1007/978-3-319-06486-4
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57. 
Cover image for Exploring Memory Hierarchy Design with Emerging Memory Technologies
Exploring Memory Hierarchy Design with Emerging Memory Technologies
Author 
Sun, Guangyu. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-00681-9
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58. 
Cover image for Parallel Computational Fluid Dynamics 25th International Conference, ParCFD 2013, Changsha, China, May 20-24, 2013. Revised Selected Papers
Parallel Computational Fluid Dynamics 25th International Conference, ParCFD 2013, Changsha, China, May 20-24, 2013. Revised Selected Papers
Author 
Li, Kenli. editor. Xiao, Zheng. editor. Wang, Yan. editor. Du, Jiayi. editor. Li, Keqin. editor.
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https://doi.org/10.1007/978-3-642-53962-6
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59. 
Cover image for Trace-Based Post-Silicon Validation for VLSI Circuits
Trace-Based Post-Silicon Validation for VLSI Circuits
Author 
Liu, Xiao. author. Xu, Qiang. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-00533-1
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60. 
Cover image for SystemC and SystemC-AMS in Practice SystemC 2.3, 2.2 and SystemC-AMS 1.0
SystemC and SystemC-AMS in Practice SystemC 2.3, 2.2 and SystemC-AMS 1.0
Author 
Banerjee, Amal. author. Sur, Balmiki. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-01147-9
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