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49. 
Cover image for Digital VLSI Systems Design A Design Manual for Implementation of Projects on FPGAs and ASICs Using Verilog
Digital VLSI Systems Design A Design Manual for Implementation of Projects on FPGAs and ASICs Using Verilog
Author 
Ramachandran, S. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-1-4020-5829-5
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50. 
Cover image for Routing Congestion in VLSI Circuits: Estimation and Optimization
Routing Congestion in VLSI Circuits: Estimation and Optimization
Author 
Saxena, Prashant. author. Shelar, Rupesh S. author. Sapatnekar, Sachin S. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/0-387-48550-3
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51. 
Cover image for Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits 2nd Edition
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits 2nd Edition
Author 
Sachdev, Manoj. editor. Gyvez, José Pineda de. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/0-387-46547-2
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52. 
Cover image for Vlsi-Soc: From Systems To Silicon Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia
Vlsi-Soc: From Systems To Silicon Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia
Author 
Reis, Ricardo. editor. Osseiran, Adam. editor. Pfleiderer, Hans-Joerg. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-73661-7
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53. 
Cover image for VLSI-SOC: From Systems to Chips IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1–3, 2003, Darmstadt, Germany
VLSI-SOC: From Systems to Chips IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1–3, 2003, Darmstadt, Germany
Author 
Glesner, Manfred. editor. Reis, Ricardo. editor. Indrusiak, Leandro. editor. Mooney, Vincent. editor. Eveking, Hans. editor.
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http://dx.doi.org/10.1007/0-387-33403-3
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54. 
Cover image for Statistical Analysis and Optimization for VLSI: Timing and Power
Statistical Analysis and Optimization for VLSI: Timing and Power
Author 
Srivastava, Ashish. author. Sylvester, Dennis. author. Blaauw, David. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/b137645
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55. 
Cover image for Frontiers of Quality Electronic Design (QED) AI, IoT and Hardware Security
Frontiers of Quality Electronic Design (QED) AI, IoT and Hardware Security
Author 
Iranmanesh, Ali. editor. SpringerLink (Online service)
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XX(520193.1)
Electronic Access 
https://doi.org/10.1007/978-3-031-16344-9
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