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49. 
Cover image for Clocking in Modern VLSI Systems
Clocking in Modern VLSI Systems
Author 
Xanthopoulos, Thucydides. editor. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-1-4419-0261-0
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50. 
Cover image for Nanometer Technology Designs High-Quality Delay Tests
Nanometer Technology Designs High-Quality Delay Tests
Author 
Tehranipoor, Mohammad. author. Ahmed, Nisar. author. SpringerLink (Online service)
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Electronic Access 
http://dx.doi.org/10.1007/978-0-387-75728-5
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51. 
Cover image for System Verilog for Verification A Guide to Learning the Testbench Language Features
System Verilog for Verification A Guide to Learning the Testbench Language Features
Author 
Spear, Chris. author. SpringerLink (Online service)
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Electronic Access 
http://dx.doi.org/10.1007/978-0-387-76530-3
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52. 
Cover image for Power Distribution Networks with On-Chip Decoupling Capacitors
Power Distribution Networks with On-Chip Decoupling Capacitors
Author 
Popovich, Mikhhail. author. Mezhiba, Andrey V. author. Friedman, Eby G. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-0-387-71601-5
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53. 
Cover image for Rapid Prototyping of Digital Systems
Rapid Prototyping of Digital Systems
Author 
Hamblen, James O. author. Hall, Tyson S. author. Furman, Michael D. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-0-387-72671-7
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54. 
Cover image for CMOS Active Inductors and Transformers Principle, Implementation, and Applications
CMOS Active Inductors and Transformers Principle, Implementation, and Applications
Author 
Yuan, Fei. author. SpringerLink (Online service)
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Electronic Access 
http://dx.doi.org/10.1007/978-0-387-76479-5
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55. 
Cover image for Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Author 
Patra, Priyardarsan. author. Kougianos, Elias. author. Ranganathan, Nagarajan. author. Mohanty, Saraju P. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-76474-0
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56. 
Cover image for Verilog and SystemVerilog Gotchas 101 Common Coding Errors and How to Avoid Them
Verilog and SystemVerilog Gotchas 101 Common Coding Errors and How to Avoid Them
Author 
Sutherland, Stuart. author. Mills, Don. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-0-387-71715-9
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57. 
Cover image for SAT-Based Scalable Formal Verification Solutions
SAT-Based Scalable Formal Verification Solutions
Author 
Ganai, Malay K. author. Gupta, Aarti. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-0-387-69167-1
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58. 
Cover image for Power-Aware Architecting for data-dominated applications
Power-Aware Architecting for data-dominated applications
Author 
Ditzel, Maarten. author. Otten, Ralph H. J. M. author. Serdijn, Wouter A. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-1-4020-6420-3
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59. 
Cover image for Writing Testbenches using System Verilog
Writing Testbenches using System Verilog
Author 
Bergeron, Janick. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/0-387-31275-7
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60. 
Cover image for Gizopoulos / Advances in ElectronicTesting
Gizopoulos / Advances in ElectronicTesting
Author 
Gizopoulos, Dimitris. editor. SpringerLink (Online service)
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Electronic Access 
http://dx.doi.org/10.1007/0-387-29409-0
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