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49. 
Cover image for Field Models in Electricity and Magnetism
Field Models in Electricity and Magnetism
Author 
Barba, Paolo. author. Savini, Antonio. author. Wiak, Slawomir. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-1-4020-6843-0
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50. 
Cover image for System Verilog for Verification A Guide to Learning the Testbench Language Features
System Verilog for Verification A Guide to Learning the Testbench Language Features
Author 
Spear, Chris. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-76530-3
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51. 
Cover image for Nanometer Technology Designs High-Quality Delay Tests
Nanometer Technology Designs High-Quality Delay Tests
Author 
Tehranipoor, Mohammad. author. Ahmed, Nisar. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-75728-5
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52. 
Cover image for Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Author 
Patra, Priyardarsan. author. Kougianos, Elias. author. Ranganathan, Nagarajan. author. Mohanty, Saraju P. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-76474-0
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53. 
Cover image for CMOS Active Inductors and Transformers Principle, Implementation, and Applications
CMOS Active Inductors and Transformers Principle, Implementation, and Applications
Author 
Yuan, Fei. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-76479-5
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54. 
Cover image for Dynamics of Microelectromechanical Systems
Dynamics of Microelectromechanical Systems
Author 
Lobontiu, Nicolae. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-68195-5
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55. 
Cover image for Closing the Power Gap Between ASIC & Custom Tools and Techniques for Low Power Design
Closing the Power Gap Between ASIC & Custom Tools and Techniques for Low Power Design
Author 
Chinnery, David. author. Keutzer, Kurt. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-68953-1
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56. 
Cover image for SAT-Based Scalable Formal Verification Solutions
SAT-Based Scalable Formal Verification Solutions
Author 
Ganai, Malay K. author. Gupta, Aarti. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-69167-1
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57. 
Cover image for Verilog and SystemVerilog Gotchas 101 Common Coding Errors and How to Avoid Them
Verilog and SystemVerilog Gotchas 101 Common Coding Errors and How to Avoid Them
Author 
Sutherland, Stuart. author. Mills, Don. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-71715-9
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58. 
Cover image for Hardware Verification with SystemVerilog An Object-Oriented Framework
Hardware Verification with SystemVerilog An Object-Oriented Framework
Author 
Mintz, Mike. author. Ekendahl, Robert. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-71740-1
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59. 
Cover image for Global Specification and Validation of Embedded Systems Integrating Heterogeneous Components
Global Specification and Validation of Embedded Systems Integrating Heterogeneous Components
Author 
Nicolescu, G. editor. Jerraya, A. A. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-6153-0
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60. 
Cover image for Full-Chip Nanometer Routing Techniques
Full-Chip Nanometer Routing Techniques
Author 
Ho, Tsung-Yi. author. Chang, Yao-Wen. author. Chen, Sao-Jie. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-6195-0
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