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49. 
Cover image for Network-on-chip : the next generation of system-on-chip integration
Network-on-chip : the next generation of system-on-chip integration
Author 
Kundu, Santanu, author. Chattopadhyay, Santanu, contributor.
Preferred Shelf Number 
TK5105.546 .K86 2015
Electronic Access 
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50. 
Cover image for Microfluidics in detection science : lab-on-a-chip technologies
Microfluidics in detection science : lab-on-a-chip technologies
Author 
Labeed, Fatime H., editor. Fatoyinbo, Henry C., editor.
Preferred Shelf Number 
ONLINE(343202.1)
Electronic Access 
ebrary An electronic book accessible through the World Wide Web; click to view
Royal Society of Chemistry http://dx.doi.org/10.1039/9781849737609
Royal Society of Chemistry http://pubs.rsc.org/en/content/ebook/978-1-84973-638-1
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51. 
Cover image for Microarchitecture of Network-on-Chip Routers A Designer's Perspective
Microarchitecture of Network-on-Chip Routers A Designer's Perspective
Author 
Dimitrakopoulos, Giorgos. author. Psarras, Anastasios. author. Seitanidis, Ioannis. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-1-4614-4301-8
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52. 
Cover image for Lab-on-a-Chip Devices and Micro-Total Analysis Systems A Practical Guide
Lab-on-a-Chip Devices and Micro-Total Analysis Systems A Practical Guide
Author 
Castillo-León, Jaime. editor. Svendsen, Winnie E. editor. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-08687-3
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53. 
Cover image for Wafer-Level Chip-Scale Packaging Analog and Power Semiconductor Applications
Wafer-Level Chip-Scale Packaging Analog and Power Semiconductor Applications
Author 
Qu, Shichun. author. Liu, Yong. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-1-4939-1556-9
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54. 
Cover image for Biological identification : DNA amplification and sequencing, optical sensing, lab-on-chip and portable systems
Biological identification : DNA amplification and sequencing, optical sensing, lab-on-chip and portable systems
Author 
Schaudies, R. Paul, editor of compilation.
Preferred Shelf Number 
ONLINE(355794.1)
Electronic Access 
ScienceDirect http://www.sciencedirect.com/science/book/9780857095015
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55. 
Cover image for Embedded Memory Design for Multi-Core and Systems on Chip
Embedded Memory Design for Multi-Core and Systems on Chip
Author 
Mohammad, Baker. author. SpringerLink (Online service)
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ONLINE
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https://doi.org/10.1007/978-1-4614-8881-1
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56. 
Cover image for Debugging Systems-on-Chip Communication-centric and Abstraction-based Techniques
Debugging Systems-on-Chip Communication-centric and Abstraction-based Techniques
Author 
Vermeulen, Bart. author. Goossens, Kees. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-06242-6
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57. 
Cover image for Designing 2D and 3D Network-on-Chip Architectures
Designing 2D and 3D Network-on-Chip Architectures
Author 
Tatas, Konstantinos. author. Siozios, Kostas. author. Soudris, Dimitrios. author. Jantsch, Axel. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-1-4614-4274-5
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58. 
Cover image for Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling
Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling
Author 
Mandal, Ayan. author. Khatri, Sunil P. author. Mahapatra, Rabi. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-1-4614-9405-8
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59. 
Cover image for Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012
Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012
Author 
Haase, Jan. editor. SpringerLink (Online service)
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ONLINE
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https://doi.org/10.1007/978-3-319-01418-0
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60. 
Cover image for VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers
Author 
Burg, Andreas. editor. Coṣkun, Ayṣe. editor. Guthaus, Matthew. editor. Katkoori, Srinivas. editor. Reis, Ricardo. editor.
Preferred Shelf Number 
ONLINE(335188.1)
Electronic Access 
http://dx.doi.org/10.1007/978-3-642-45073-0
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