Search Results for Systems engineering.

12 Results Found

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Facing the Multicore-Challenge III Aspects of New Paradigms and Technologies in Parallel Computing

Author

Keller, Rainer. editor. Kramer, David. editor. Weiss, Jan-Philipp. editor. SpringerLink (Online service)

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ONLINE(334079.1)

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http://dx.doi.org/10.1007/978-3-642-35893-7

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Memory Controllers for Real-Time Embedded Systems Predictable and Composable Real-Time Systems

Author

Akesson, Benny. author. Goossens, Kees. author. SpringerLink (Online service)

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ONLINE

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http://dx.doi.org/10.1007/978-1-4419-8207-0

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Emerging Technologies and Circuits

Author

Amara, Amara. editor. Ea, Thomas. editor. Belleville, Marc. editor. SpringerLink (Online service)

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ONLINE

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http://dx.doi.org/10.1007/978-90-481-9379-0

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Embedded Memories for Nano-Scale VLSIs

Author

Zhang, Kevin. editor. SpringerLink (Online service)

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ONLINE

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http://dx.doi.org/10.1007/978-0-387-88497-4

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Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers

Author

Svensson, Lars. editor. Monteiro, José. editor. SpringerLink (Online service)

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ONLINE

Electronic Access

http://dx.doi.org/10.1007/978-3-540-95948-9

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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Process-Aware SRAM Design and Test

Author

Pavlov, Andrei. author. Sachdev, Manoj. author. SpringerLink (Online service)

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ONLINE

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http://dx.doi.org/10.1007/978-1-4020-8363-1

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Memories in Wireless Systems

Author

Micheloni, Rino. editor. Campardo, Giovanni. editor. Olivo, Piero. editor. SpringerLink (Online service)

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ONLINE

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http://dx.doi.org/10.1007/978-3-540-79078-5

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Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings

Author

Azémard, Nadine. editor. Svensson, Lars. editor. SpringerLink (Online service)

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ONLINE

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http://dx.doi.org/10.1007/978-3-540-74442-9

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Ultra-Low Voltage Nano-Scale Memories

Author

Itoh, Kiyoo. editor. Horiguchi, Masashi. editor. Tanaka, Hitoshi. editor. SpringerLink (Online service)

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ONLINE

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http://dx.doi.org/10.1007/978-0-387-68853-4

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10.

Co-design for System Acceleration A Quantitative Approach

Author

Nedjah, Nadia. author. Mourelle, Luiza De Macedo. author. SpringerLink (Online service)

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ONLINE

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http://dx.doi.org/10.1007/978-1-4020-5546-1

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11.

Advanced Memory Optimization Techniques for Low-Power Embedded Processors

Author

Verma, Manish. author. Marwedel, Peter. author. SpringerLink (Online service)

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ONLINE

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http://dx.doi.org/10.1007/978-1-4020-5897-4

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12.

Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings

Author

Vounckx, Johan. editor. Azemard, Nadine. editor. Maurine, Philippe. editor. SpringerLink (Online service)

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ONLINE

Electronic Access

http://dx.doi.org/10.1007/11847083

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