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1. 
Cover image for Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog
Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog
Author 
Taraate, Vaibbhav. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-981-10-8776-9
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2. 
Cover image for On the Physical Security of Physically Unclonable Functions
On the Physical Security of Physically Unclonable Functions
Author 
Tajik, Shahin. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-75820-6
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3. 
Cover image for A Tutorial Introduction to VHDL Programming
A Tutorial Introduction to VHDL Programming
Author 
Gazi, Orhan. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-981-13-2309-6
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4. 
Cover image for Test Generation of Crosstalk Delay Faults in VLSI Circuits
Test Generation of Crosstalk Delay Faults in VLSI Circuits
Author 
Jayanthy, S. author. Bhuvaneswari, M.C. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-981-13-2493-2
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5. 
Cover image for Optimal Design of Distributed Control and Embedded Systems
Optimal Design of Distributed Control and Embedded Systems
Author 
Çela, Arben. author. Ben Gaid, Mongi. author. Li, Xu-Guang. author. Niculescu, Silviu-Iulian. author. SpringerLink (Online service)
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ONLINE
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https://doi.org/10.1007/978-3-319-02729-6
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