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Subject: Logic design.

Author

SpringerLink (Online service)

(11)

Das, Vinu V. editor.

(2)

Thankachan, Nessy. editor.

(2)

Barkalov, Alexander. author.

(1)

Barkalov, Alexander. editor.

(1)

Bertels, Koen. editor. (orcid)0000-0001-9310-4885

(1)

Bitsch, Friedemann. editor. (orcid)0000-0001-6152-4121

(1)

Debnath, Narayan C. editor.

(1)

Dubey, Rahul. author.

(1)

Elfadel, Ibrahim (Abe) M. editor. (orcid)0000-0003-3220-9987

(1)

Gallina, Barbara. editor. (orcid)0000-0002-6952-1053

(1)

Kaeli, David. editor.

(1)

Leuken, René. editor.

(1)

Maniatakos, Michail. editor. (orcid)0000-0001-6899-0651

(1)

Monteiro, José. editor.

(1)

Monteiro, José. editor. (orcid)0000-0003-0603-2268

(1)

Reis, Ricardo. editor. (orcid)0000-0001-5781-5858

(1)

Sachs, Kai. editor.

(1)

Schulte, Michael. editor. (orcid)0000-0002-0213-4155

(1)

Silvano, Cristina. editor. (orcid)0000-0003-1668-0883

(1)

Skavhaug, Amund. editor.

(1)

Sonza Reorda, Matteo. editor. (orcid)0000-0003-2899-7669

(1)

Stephen, Janahanlal. editor.

(1)

Taraate, Vaibbhav. author.

(1)

Titarenko, Larysa. author.

(1)

Titarenko, Larysa. editor.

(1)

Ugurdag, H. Fatih. editor. (orcid)0000-0002-6256-0850

(1)

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Subject

Microprogramming.

(8)

Computer science.

(4)

Computer hardware.

(3)

(3)

Microprogramming .

(3)

Software engineering.

(3)

Systems engineering.

(3)

(2)

(2)

Memory management (Computer science).

(2)

Operating systems (Computers).

(2)

Application software.

(1)

Arithmetic and logic units, Computer.

(1)

Computer Communication Networks.

(1)

Computer aided design.

(1)

Computer organization.

(1)

Computer security.

(1)

Computer simulation.

(1)

Computer system performance.

(1)

Control engineering systems.

(1)

Electronic circuits.

(1)

Programming languages (Electronic computers).

(1)

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1.

Cover image for Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog

Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog

Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog

Author

Taraate, Vaibbhav. author. SpringerLink (Online service)

Preferred Shelf Number

ONLINE

Electronic Access

https://doi.org/10.1007/978-981-10-8776-9

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2.

Cover image for Transactions on High-Performance Embedded Architectures and Compilers V

Transactions on High-Performance Embedded Architectures and Compilers V

Transactions on High-Performance Embedded Architectures and Compilers V

Author

Silvano, Cristina. editor. (orcid)0000-0003-1668-0883 Bertels, Koen. editor. (orcid)0000-0001-9310-4885 Schulte, Michael. editor. (orcid)0000-0002-0213-4155 SpringerLink (Online service)

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ONLINE

Electronic Access

https://doi.org/10.1007/978-3-662-58834-5

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3.

Cover image for VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23–25, 2017, Revised and Extended Selected Papers

VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23–25, 2017, Revised and Extended Selected Papers

VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23–25, 2017, Revised and Extended Selected Papers

Author

Maniatakos, Michail. editor. (orcid)0000-0001-6899-0651 Elfadel, Ibrahim (Abe) M. editor. (orcid)0000-0003-3220-9987 Sonza Reorda, Matteo. editor. (orcid)0000-0003-2899-7669 Ugurdag, H. Fatih. editor. (orcid)0000-0002-6256-0850 Monteiro, José. editor. (orcid)0000-0003-0603-2268

Preferred Shelf Number

ONLINE

Electronic Access

https://doi.org/10.1007/978-3-030-15663-3

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4.

Cover image for Computer Safety, Reliability, and Security 37th International Conference, SAFECOMP 2018, Västerås, Sweden, September 19-21, 2018, Proceedings

Computer Safety, Reliability, and Security 37th International Conference, SAFECOMP 2018, Västerås, Sweden, September 19-21, 2018, Proceedings

Computer Safety, Reliability, and Security 37th International Conference, SAFECOMP 2018, Västerås, Sweden, September 19-21, 2018, Proceedings

Author

Gallina, Barbara. editor. (orcid)0000-0002-6952-1053 Skavhaug, Amund. editor. Bitsch, Friedemann. editor. (orcid)0000-0001-6152-4121 SpringerLink (Online service)

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Electronic Access

https://doi.org/10.1007/978-3-319-99130-6

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5.

Cover image for Power Electronics and Instrumentation Engineering International Conference, PEIE 2010, Kochi, Kerala, India, September 7-9, 2010. Proceedings

Power Electronics and Instrumentation Engineering International Conference, PEIE 2010, Kochi, Kerala, India, September 7-9, 2010. Proceedings

Power Electronics and Instrumentation Engineering International Conference, PEIE 2010, Kochi, Kerala, India, September 7-9, 2010. Proceedings

Author

Das, Vinu V. editor. Stephen, Janahanlal. editor. Thankachan, Nessy. editor. SpringerLink (Online service)

Preferred Shelf Number

ONLINE

Electronic Access

http://dx.doi.org/10.1007/978-3-642-15739-4

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6.

Cover image for Advances in Power Electronics and Instrumentation Engineering Second International Conference, PEIE 2011, Nagpur, Maharashtra, India, April 21-22, 2011. Proceedings

Advances in Power Electronics and Instrumentation Engineering Second International Conference, PEIE 2011, Nagpur, Maharashtra, India, April 21-22, 2011. Proceedings

Advances in Power Electronics and Instrumentation Engineering Second International Conference, PEIE 2011, Nagpur, Maharashtra, India, April 21-22, 2011. Proceedings

Author

Das, Vinu V. editor. Thankachan, Nessy. editor. Debnath, Narayan C. editor. SpringerLink (Online service)

Preferred Shelf Number

ONLINE

Electronic Access

http://dx.doi.org/10.1007/978-3-642-20499-9

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7.

Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers

Author

Monteiro, José. editor. Leuken, René. editor. SpringerLink (Online service)

Preferred Shelf Number

ONLINE

Electronic Access

http://dx.doi.org/10.1007/978-3-642-11802-9

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8.

Cover image for Computer Performance Evaluation and Benchmarking SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009. Proceedings

Computer Performance Evaluation and Benchmarking SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009. Proceedings

Computer Performance Evaluation and Benchmarking SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009. Proceedings

Author

Kaeli, David. editor. Sachs, Kai. editor. SpringerLink (Online service)

Preferred Shelf Number

ONLINE

Electronic Access

http://dx.doi.org/10.1007/978-3-540-93799-9

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9.

Cover image for Logic Synthesis for FSM-Based Control Units

Logic Synthesis for FSM-Based Control Units

Logic Synthesis for FSM-Based Control Units

Author

Barkalov, Alexander. author. Titarenko, Larysa. author. SpringerLink (Online service)

Preferred Shelf Number

ONLINE

Electronic Access

http://dx.doi.org/10.1007/978-3-642-04309-3

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10.

Cover image for Introduction to Embedded System Design Using Field Programmable Gate Arrays

Introduction to Embedded System Design Using Field Programmable Gate Arrays

Introduction to Embedded System Design Using Field Programmable Gate Arrays

Author

Dubey, Rahul. author. SpringerLink (Online service)

Preferred Shelf Number

ONLINE

Electronic Access

http://dx.doi.org/10.1007/978-1-84882-016-6

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11.

Cover image for Logic Synthesis for Compositional Microprogram Control Units

Logic Synthesis for Compositional Microprogram Control Units

Logic Synthesis for Compositional Microprogram Control Units

Author

Barkalov, Alexander. editor. Titarenko, Larysa. editor. SpringerLink (Online service)

Preferred Shelf Number

ONLINE

Electronic Access

http://dx.doi.org/10.1007/978-3-540-69285-0

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1

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