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1. 
Cover image for Semiconductor Modeling For Simulating Signal, Power, and Electromagnetic Integrity
Semiconductor Modeling For Simulating Signal, Power, and Electromagnetic Integrity
Author 
Leventhal, Roy G. author. Green, Lynne. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/b104647
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2. 
Cover image for Verification Methodology Manual for SystemVerilog
Verification Methodology Manual for SystemVerilog
Author 
Bergeron, Janick. author. Cerny, Eduard. author. Hunter, Alan. author. Nightingale, Andrew. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/b135575
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3. 
Cover image for Systemverilog for Verification A Guide to Learning the Testbench Language Features
Systemverilog for Verification A Guide to Learning the Testbench Language Features
Author 
Spear, Chris. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/b138536
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4. 
Cover image for Writing Testbenches using System Verilog
Writing Testbenches using System Verilog
Author 
Bergeron, Janick. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/0-387-31275-7
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5. 
Cover image for Abstraction Refinement for Large Scale Model Checking
Abstraction Refinement for Large Scale Model Checking
Author 
Wang, Chao. author. Hachtel, Gary D. author. Somenzi, Fabio. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/0-387-34600-7
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6. 
Cover image for A Practical Introduction to PSL
A Practical Introduction to PSL
Author 
Eisner, Cindy. author. Fisman, Dana. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-0-387-36123-9
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7. 
Cover image for Hardware Verification with C++ A Practitioner’s Handbook
Hardware Verification with C++ A Practitioner’s Handbook
Author 
Mintz, Mike. author. Ekendahl, Robert. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-0-387-36254-0
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8. 
Cover image for SystemVerilog for Design A Guide to Using SystemVerilog for Hardware Design and Modeling
SystemVerilog for Design A Guide to Using SystemVerilog for Hardware Design and Modeling
Author 
Sutherland, Stuart. author. Davidmann, Simon. author. Flake, Peter. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/0-387-36495-1
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9. 
Cover image for A Roadmap for Formal Property Verification
A Roadmap for Formal Property Verification
Author 
DasGupta, Pallab. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-1-4020-4758-9
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10. 
Cover image for Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
Author 
Kogel, Tim. author. Leupers, Rainer. author. Meyr, Heinrich. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/1-4020-4826-2
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11. 
Cover image for Layoutsynthese elektronischer Schaltungen — Grundlegende Algorithmen für die Entwurfsautomatisierung
Layoutsynthese elektronischer Schaltungen — Grundlegende Algorithmen für die Entwurfsautomatisierung
Author 
Lienig, Jens. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/3-540-29942-4
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12. 
Cover image for Rapid Prototyping of Digital Systems
Rapid Prototyping of Digital Systems
Author 
Hamblen, James O. author. Hall, Tyson S. author. Furman, Michael D. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/0-387-28965-8
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