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1. 
Cover image for Digital VLSI Systems Design A Design Manual for Implementation of Projects on FPGAs and ASICs Using Verilog
Digital VLSI Systems Design A Design Manual for Implementation of Projects on FPGAs and ASICs Using Verilog
Author 
Ramachandran, S. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-1-4020-5829-5
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2. 
Cover image for Real-Time Applications with Stochastic Task Execution Times Analysis and Optimisation
Real-Time Applications with Stochastic Task Execution Times Analysis and Optimisation
Author 
Manolache, Sorin. author. Eles, Petru. author. Peng, Zebo. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/1-4020-5509-9
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3. 
Cover image for Processor Design System-on-Chip Computing for ASICs and FPGAs
Processor Design System-on-Chip Computing for ASICs and FPGAs
Author 
Nurmi, Jari. editor. SpringerLink (Online service)
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ONLINE
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http://dx.doi.org/10.1007/978-1-4020-5530-0
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4. 
Cover image for Real-Time Object Uniform Design Methodology with UML
Real-Time Object Uniform Design Methodology with UML
Author 
Duc, Bui Minh. editor. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-1-4020-5977-3
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5. 
Cover image for Exploring C for Microcontrollers A Hands on Approach
Exploring C for Microcontrollers A Hands on Approach
Author 
Parab, Jivan S. author. Shelake, Vinod G. author. Kamat, Rajanish K. author. Naik, Gourish M. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-6067-0
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6. 
Cover image for Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems Proceedings of the GM R&D Workshop, Bangalore, India, January 2007
Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems Proceedings of the GM R&D Workshop, Bangalore, India, January 2007
Author 
Ramesh, S. editor. Sampath, Prahladavaradan. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-6254-4
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7. 
Cover image for Optimized ASIP Synthesis from Architecture Description Language Models
Optimized ASIP Synthesis from Architecture Description Language Models
Author 
Schliebusch, Oliver. author. Meyr, Heinrich. author. Leupers, Rainer. author. SpringerLink (Online service)
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ONLINE
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http://dx.doi.org/10.1007/978-1-4020-5686-4
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8. 
Cover image for Cryptographic Algorithms on Reconfigurable Hardware
Cryptographic Algorithms on Reconfigurable Hardware
Author 
Rodríguez-Henríquez, Francisco. author. Pérez, Arturo Díaz. author. Saqib, Nazar Abbas. author. Koç, Çetin Kaya. author. SpringerLink (Online service)
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ONLINE
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http://dx.doi.org/10.1007/978-0-387-36682-1
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9. 
Cover image for Ultra-Low Voltage Nano-Scale Memories
Ultra-Low Voltage Nano-Scale Memories
Author 
Itoh, Kiyoo. editor. Horiguchi, Masashi. editor. Tanaka, Hitoshi. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-68853-4
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10. 
Cover image for Hardware Verification with SystemVerilog An Object-Oriented Framework
Hardware Verification with SystemVerilog An Object-Oriented Framework
Author 
Mintz, Mike. author. Ekendahl, Robert. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-71740-1
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11. 
Cover image for Designing Embedded Processors A Low Power Perspective
Designing Embedded Processors A Low Power Perspective
Author 
Henkel, Jörg. editor. Parameswaran, Sri. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-5869-1
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12. 
Cover image for Advanced Memory Optimization Techniques for Low-Power Embedded Processors
Advanced Memory Optimization Techniques for Low-Power Embedded Processors
Author 
Verma, Manish. author. Marwedel, Peter. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-5897-4
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