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1. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings
Author 
Azémard, Nadine. editor. Svensson, Lars. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-3-540-74442-9
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2. 
Cover image for Computational Intelligence for Engineering and Manufacturing
Computational Intelligence for Engineering and Manufacturing
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Andina, Diego. editor. Pham, Duc Truong. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/0-387-37452-3
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3. 
Cover image for Ultra-Low Voltage Nano-Scale Memories
Ultra-Low Voltage Nano-Scale Memories
Author 
Itoh, Kiyoo. editor. Horiguchi, Masashi. editor. Tanaka, Hitoshi. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-68853-4
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4. 
Cover image for SAT-Based Scalable Formal Verification Solutions
SAT-Based Scalable Formal Verification Solutions
Author 
Ganai, Malay K. author. Gupta, Aarti. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-69167-1
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5. 
Cover image for Hardware Verification with SystemVerilog An Object-Oriented Framework
Hardware Verification with SystemVerilog An Object-Oriented Framework
Author 
Mintz, Mike. author. Ekendahl, Robert. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-71740-1
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6. 
Cover image for Vlsi-Soc: From Systems To Silicon Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia
Vlsi-Soc: From Systems To Silicon Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia
Author 
Reis, Ricardo. editor. Osseiran, Adam. editor. Pfleiderer, Hans-Joerg. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-73661-7
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7. 
Cover image for Optimized ASIP Synthesis from Architecture Description Language Models
Optimized ASIP Synthesis from Architecture Description Language Models
Author 
Schliebusch, Oliver. author. Meyr, Heinrich. author. Leupers, Rainer. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-5686-4
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8. 
Cover image for Digital VLSI Systems Design A Design Manual for Implementation of Projects on FPGAs and ASICs Using Verilog
Digital VLSI Systems Design A Design Manual for Implementation of Projects on FPGAs and ASICs Using Verilog
Author 
Ramachandran, S. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-5829-5
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9. 
Cover image for Systems engineering with SysML/UML modeling, analysis, design
Systems engineering with SysML/UML modeling, analysis, design
Author 
Weilkiens, Tim.
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ScienceDirect http://www.sciencedirect.com/science/book/9780123742742
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10. 
Cover image for Cryptographic Algorithms on Reconfigurable Hardware
Cryptographic Algorithms on Reconfigurable Hardware
Author 
Rodríguez-Henríquez, Francisco. author. Pérez, Arturo Díaz. author. Saqib, Nazar Abbas. author. Koç, Çetin Kaya. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-36682-1
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11. 
Cover image for Processor Design System-on-Chip Computing for ASICs and FPGAs
Processor Design System-on-Chip Computing for ASICs and FPGAs
Author 
Nurmi, Jari. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-5530-0
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12. 
Cover image for Cognitive Radio, Software Defined Radio, and Adaptive Wireless Systems
Cognitive Radio, Software Defined Radio, and Adaptive Wireless Systems
Author 
Arslan, Hüseyin. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-5542-3
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