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1. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers
Author 
Svensson, Lars. editor. Monteiro, José. editor. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-3-540-95948-9
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2. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings
Author 
Azémard, Nadine. editor. Svensson, Lars. editor. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-3-540-74442-9
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3. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings
Author 
Vounckx, Johan. editor. Azemard, Nadine. editor. Maurine, Philippe. editor. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/11847083
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4. 
Cover image for Reliable and Energy Efficient Streaming Multiprocessor Systems
Reliable and Energy Efficient Streaming Multiprocessor Systems
Author 
Das, Anup Kumar. author. Kumar, Akash. author. Veeravalli, Bharadwaj. author. Catthoor, Francky. author. SpringerLink (Online service)
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Electronic Access 
https://doi.org/10.1007/978-3-319-69374-3
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5. 
Cover image for Design of FPGA-Based Computing Systems with OpenCL
Design of FPGA-Based Computing Systems with OpenCL
Author 
Waidyasooriya, Hasitha Muthumala. author. Hariyama, Masanori. author. Uchiyama, Kunio. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-68161-0
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6. 
Cover image for Simulation and Optimization of Digital Circuits Considering and Mitigating Destabilizing Factors
Simulation and Optimization of Digital Circuits Considering and Mitigating Destabilizing Factors
Author 
Melikyan, Vazgen. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-71637-4
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7. 
Cover image for ASIC/SoC Functional Design Verification A Comprehensive Guide to Technologies and Methodologies
ASIC/SoC Functional Design Verification A Comprehensive Guide to Technologies and Methodologies
Author 
Mehta, Ashok B. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-59418-7
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8. 
Cover image for Design, Analysis and Test of Logic Circuits Under Uncertainty
Design, Analysis and Test of Logic Circuits Under Uncertainty
Author 
Krishnaswamy, Smita. author. Markov, Igor L. author. Hayes, John P. author. SpringerLink (Online service)
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ONLINE(335669.1)
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http://dx.doi.org/10.1007/978-90-481-9644-9
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9. 
Cover image for Logic Functions and Equations Examples and Exercises
Logic Functions and Equations Examples and Exercises
Author 
Steinbach, Bernd. author. Posthoff, Christian. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-1-4020-9595-5
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10. 
Cover image for High-Level Synthesis From Algorithm to Digital Circuit
High-Level Synthesis From Algorithm to Digital Circuit
Author 
Coussy, Philippe. editor. Morawiec, Adam. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-8588-8
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11. 
Cover image for A Roadmap for Formal Property Verification
A Roadmap for Formal Property Verification
Author 
DasGupta, Pallab. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-4758-9
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