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1. 
Cover image for Metal casting : computer-aided design and analysis
Metal casting : computer-aided design and analysis
Author 
Ravi, B., author.
Preferred Shelf Number 
TS230 R38 2006
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Cover image for Computer aided design, engineering, and manufacturing systems techniques and applications
Computer aided design, engineering, and manufacturing systems techniques and applications
Author 
Leondes, Cornelius T.
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3. 
Cover image for Computer aided design, engineering, and manufacturing systems techniques and applications
Computer aided design, engineering, and manufacturing systems techniques and applications
Author 
Leondes, Cornelius T.
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ONLINE
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Cover image for Computer aided design, engineering, and manufacturing systems techniques and applications
Computer aided design, engineering, and manufacturing systems techniques and applications
Author 
Leondes, Cornelius T.
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ONLINE
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5. 
Cover image for CATIA V5 Workbook, releases 16
CATIA V5 Workbook, releases 16
Author 
Cozzens, Richard. Metalcraft Technologies, Inc.
Preferred Shelf Number 
TA345.5.C3 C69 2006
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6. 
Cover image for Advanced CATIA V5 workbook : release 16
Advanced CATIA V5 workbook : release 16
Author 
Cozzens, Richard.
Preferred Shelf Number 
TA345.5.C3 C69 2006
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7. 
Cover image for Large-scale 3D data integration
Large-scale 3D data integration
Author 
Zlatanova, Siyka. Prosperi, David.
Preferred Shelf Number 
TA174 .L37 2006
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8. 
Cover image for Electromagnetic Compatibility of Integrated Circuits Techniques for low emission and susceptibility
Electromagnetic Compatibility of Integrated Circuits Techniques for low emission and susceptibility
Author 
Ben Dhia, Sonia. editor. Ramdani, Mohamed. editor. Sicard, Etienne. editor. SpringerLink (Online service)
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ONLINE
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http://dx.doi.org/10.1007/b137864
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9. 
Cover image for Systemverilog for Verification A Guide to Learning the Testbench Language Features
Systemverilog for Verification A Guide to Learning the Testbench Language Features
Author 
Spear, Chris. author. SpringerLink (Online service)
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ONLINE
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http://dx.doi.org/10.1007/b138536
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10. 
Cover image for Writing Testbenches using System Verilog
Writing Testbenches using System Verilog
Author 
Bergeron, Janick. author. SpringerLink (Online service)
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ONLINE
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http://dx.doi.org/10.1007/0-387-31275-7
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11. 
Cover image for Interconnect Noise Optimization in Nanometer Technologies
Interconnect Noise Optimization in Nanometer Technologies
Author 
Elgamel, Mohamed A. author. Bayoumi, Magdy A. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/0-387-29366-3
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12. 
Cover image for Constraint-Based Verification
Constraint-Based Verification
Author 
Yuan, Jun. author. Pixley, Carl. author. Aziz, Adnan. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/0-387-30784-2
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