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1. 
Cover image for Languages, Design Methods, and Tools for Electronic System Design Selected Contributions from FDL 2017
Languages, Design Methods, and Tools for Electronic System Design Selected Contributions from FDL 2017
Author 
Große, Daniel. editor. Vinco, Sara. editor. Patel, Hiren. editor. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-030-02215-0
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2. 
Cover image for Languages, Design Methods, and Tools for Electronic System Design Selected Contributions from FDL 2013
Languages, Design Methods, and Tools for Electronic System Design Selected Contributions from FDL 2013
Author 
Louërat, Marie-Minerve. editor. Maehne, Torsten. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-06317-1
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3. 
Cover image for Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012
Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012
Author 
Haase, Jan. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-01418-0
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4. 
Cover image for Spintronics-based Computing
Spintronics-based Computing
Author 
Zhao, Weisheng. editor. Prenat, Guillaume. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-15180-9
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5. 
Cover image for Three-Dimensional Design Methodologies for Tree-based FPGA Architecture
Three-Dimensional Design Methodologies for Tree-based FPGA Architecture
Author 
Pangracious, Vinod. author. Marrakchi, Zied. author. Mehrez, Habib. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-19174-4
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6. 
Cover image for Multi-Net Optimization of VLSI Interconnect
Multi-Net Optimization of VLSI Interconnect
Author 
Moiseev, Konstantin. author. Kolodny, Avinoam. author. Wimer, Shmuel. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-1-4614-0821-5
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7. 
Cover image for Engineering Embedded Systems Physics, Programs, Circuits
Engineering Embedded Systems Physics, Programs, Circuits
Author 
Hintenaus, Peter. author. SpringerLink (Online service)
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ONLINE
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https://doi.org/10.1007/978-3-319-10680-9
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8. 
Cover image for Design of cost-efficient interconnect processing units : Spidergon STNoC
Design of cost-efficient interconnect processing units : Spidergon STNoC
Author 
Coppola, Marcello.
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TK5105.546 .D47 2009
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9. 
Cover image for Memory, microprocessor, and ASIC
Memory, microprocessor, and ASIC
Author 
Chen, Wai-Kai, 1936-
Preferred Shelf Number 
TK7895 .M4 V57 2003
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