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Cover image for Verilog digital system design RT level synthesis, testbench, and verification
Verilog digital system design RT level synthesis, testbench, and verification
Author 
Navabi, Zainalabedin.
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ONLINE
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2. 
Cover image for Fundamentals of digital logic with Verilog design
Fundamentals of digital logic with Verilog design
Author 
Brown, Stephen D. Vranesic, Zvonko G., ort. yaz.
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TK7868.L6 B76 2004
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Beytepe Library~2
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3. 
Cover image for Verilog coding for logic synthesis
Verilog coding for logic synthesis
Author 
Lee, Weng Fook. John Wiley & Sons, Inc.
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ONLINE
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Available by subscription from Safari Books Online
http://catdir.loc.gov/catdir/bios/wiley045/2002032433.html
John Wiley http://dx.doi.org/10.1002/0471457566
http://www3.interscience.wiley.com.ezlibproxy1.ntu.edu.sg/cgi-bin/bookhome/109855736
Book review (E-STREAMS) http://www.e-streams.com/es0704/es0704%5F3161.html
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