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1. 
Cover image for Hardware Based Packet Classification for High Speed Internet Routers
Hardware Based Packet Classification for High Speed Internet Routers
Author 
Meiners, Chad R. author. Liu, Alex X. author. Torng, Eric. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-6700-8
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2. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers
Author 
Monteiro, José. editor. Leuken, René. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-3-642-11802-9
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3. 
Cover image for Embedded Memories for Nano-Scale VLSIs
Embedded Memories for Nano-Scale VLSIs
Author 
Zhang, Kevin. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-88497-4
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4. 
Cover image for Co-design for System Acceleration A Quantitative Approach
Co-design for System Acceleration A Quantitative Approach
Author 
Nedjah, Nadia. author. Mourelle, Luiza De Macedo. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-5546-1
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5. 
Cover image for Ultra-Low Voltage Nano-Scale Memories
Ultra-Low Voltage Nano-Scale Memories
Author 
Itoh, Kiyoo. editor. Horiguchi, Masashi. editor. Tanaka, Hitoshi. editor. SpringerLink (Online service)
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Electronic Access 
http://dx.doi.org/10.1007/978-0-387-68853-4
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