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1. 
Cover image for Direct Transistor-level Layout for Digital Blocks
Direct Transistor-level Layout for Digital Blocks
Author 
Gopalakrishnan, Prakash. author. Rutenbar, Rob A. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/b117054
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2. 
Cover image for Analytical Modelling of Breakdown Effect in Graphene Nanoribbon Field Effect Transistor
Analytical Modelling of Breakdown Effect in Graphene Nanoribbon Field Effect Transistor
Author 
Amiri, Iraj Sadegh. author. Ghadiry, Mahdiar. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-981-10-6550-7
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3. 
Cover image for Planar Double-Gate Transistor From Technology to Circuit
Planar Double-Gate Transistor From Technology to Circuit
Author 
Amara, Amara. editor. Rozeau, Olivier. editor. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-1-4020-9341-8
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4. 
Cover image for TRANSISTOR LEVEL MODELING FOR ANALOG/RF IC DESIGN
TRANSISTOR LEVEL MODELING FOR ANALOG/RF IC DESIGN
Author 
GRABINSKI, WLADYSLAW. editor. NAUWELAERS, BART. editor. SCHREURS, DOMINIQUE. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/1-4020-4556-5
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