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1. 
Cover image for Routing Algorithms in Networks-on-Chip
Routing Algorithms in Networks-on-Chip
Author 
Palesi, Maurizio. editor. Daneshtalab, Masoud. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-1-4614-8274-1
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2. 
Cover image for Pipelined Multiprocessor System-on-Chip for Multimedia
Pipelined Multiprocessor System-on-Chip for Multimedia
Author 
Javaid, Haris. author. Parameswaran, Sri. author. SpringerLink (Online service)
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Electronic Access 
https://doi.org/10.1007/978-3-319-01113-4
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3. 
Cover image for Security Policy in System-on-Chip Designs Specification, Implementation and Verification
Security Policy in System-on-Chip Designs Specification, Implementation and Verification
Author 
Ray, Sandip. author. Basak, Abhishek. author. Bhunia, Swarup. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-93464-8
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4. 
Cover image for Debugging Systems-on-Chip Communication-centric and Abstraction-based Techniques
Debugging Systems-on-Chip Communication-centric and Abstraction-based Techniques
Author 
Vermeulen, Bart. author. Goossens, Kees. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-06242-6
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5. 
Cover image for Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling
Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling
Author 
Mandal, Ayan. author. Khatri, Sunil P. author. Mahapatra, Rabi. author. SpringerLink (Online service)
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ONLINE
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https://doi.org/10.1007/978-1-4614-9405-8
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6. 
Cover image for Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012
Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012
Author 
Haase, Jan. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-01418-0
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7. 
Cover image for Single- and multi-chip microcontroller interfacing for the Motorola 68HC12
Single- and multi-chip microcontroller interfacing for the Motorola 68HC12
Author 
Lipovski, G. Jack.
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ScienceDirect http://www.sciencedirect.com/science/book/9780124518308
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8. 
Cover image for Design of cost-efficient interconnect processing units Spidergon STNoC
Design of cost-efficient interconnect processing units Spidergon STNoC
Author 
Coppola, Marcello.
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Distributed by publisher. Purchase or institutional license may be required for access.
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