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1. 
Cover image for On-Chip Training NPU - Algorithm, Architecture and SoC Design
On-Chip Training NPU - Algorithm, Architecture and SoC Design
Author 
Han, Donghyeon. author. Yoo, Hoi-Jun. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-031-34237-0
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2. 
Cover image for Explainable machine learning models and architectures
Explainable machine learning models and architectures
Author 
Tripathi, Suman Lata, editor. Mahmud, Mufti, editor.
Preferred Shelf Number 
Q325.5 .E98 2023
Electronic Access 
https://onlinelibrary.wiley.com/doi/book/10.1002/9781394186570
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3. 
Cover image for Engineering Applications of FPGAs Chaotic Systems, Artificial Neural Networks, Random Number Generators, and Secure Communication Systems
Engineering Applications of FPGAs Chaotic Systems, Artificial Neural Networks, Random Number Generators, and Secure Communication Systems
Author 
Tlelo-Cuautle, Esteban. author. (orcid)0000-0001-7187-4686 Rangel-Magdaleno, José de Jesús. author. de la Fraga, Luis Gerardo. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-34115-6
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Availability 
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