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Cover image for Verilog coding for logic synthesis
Verilog coding for logic synthesis
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Lee, Weng Fook. John Wiley & Sons, Inc.
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John Wiley http://dx.doi.org/10.1002/0471457566
http://www3.interscience.wiley.com.ezlibproxy1.ntu.edu.sg/cgi-bin/bookhome/109855736
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2. 
Cover image for Mechatronic systems modelling and simulation with HDLs
Mechatronic systems modelling and simulation with HDLs
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Pelz, Georg, 1962- John Wiley & Sons. Wiley InterScience (Online service)
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John Wiley http://dx.doi.org/10.1002/0470867906
John Wiley http://dx.doi.org/10.1002/9780470867907
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3. 
Cover image for The system designer's guide to VHDL-AMS analog, mixed-signal, and mixed-technology modeling
The system designer's guide to VHDL-AMS analog, mixed-signal, and mixed-technology modeling
Author 
Ashenden, Peter J. Peterson, Gregory D. Teegarden, Darrell A.
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ScienceDirect http://www.sciencedirect.com/science/book/9781558607491
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