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1. 
Cover image for Explainable machine learning models and architectures
Explainable machine learning models and architectures
Author 
Tripathi, Suman Lata, editor. Mahmud, Mufti, editor.
Preferred Shelf Number 
Q325.5 .E98 2023
Electronic Access 
https://onlinelibrary.wiley.com/doi/book/10.1002/9781394186570
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2. 
Cover image for Formal Verification of Simulink/Stateflow Diagrams A Deductive Approach
Formal Verification of Simulink/Stateflow Diagrams A Deductive Approach
Author 
Zhan, Naijun. author. Wang, Shuling. author. (orcid)0000-0002-2798-2660 Zhao, Hengjun. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-47016-0
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3. 
Cover image for SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applications
SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applications
Author 
Mehta, Ashok B. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-30539-4
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4. 
Cover image for SVA: The Power of Assertions in SystemVerilog
SVA: The Power of Assertions in SystemVerilog
Author 
Cerny, Eduard. author. Dudani, Surrendra. author. Havlicek, John. author. Korchemny, Dmitry. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-07139-8
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